Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

spi_controller

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 677kb
  • Downloaded :0次
  • Author :w***
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Download1 Download2
Don't use download software fo downloading.
If download fail,Try it again for free.
Introduction - If you have any usage issues, please Google them yourself
Spi master controller design example, total structure design, test procedures
Packet file list
(Preview for download)
spi_controller
..............\bench.vcd
..............\chart
..............\.....\Thumbs.db
..............\.....\图6-11.bmp
..............\.....\图6-12.bmp
..............\.....\图6-13.bmp
..............\.....\图6-14.bmp
..............\.....\图6-17.bmp
..............\.....\图6-18.bmp
..............\.....\图6-19.bmp
..............\.....\图6-7.bmp
..............\spi_clgen.v
..............\spi_controller.cr.mti
..............\spi_controller.mpf
..............\spi_defines.v
..............\spi_shift.v
..............\spi_slave_model.v
..............\spi_top.v
..............\tb_spi_top.v
..............\timescale.v
..............\transcript
..............\vsim.wlf
..............\wave
..............\....\spi_clgen.bmp
..............\....\spi_shift.bmp
..............\....\spi_slave_model.bmp
..............\....\spi_top.bmp
..............\....\tb_spi_top.bmp
..............\....\Thumbs.db
..............\....\wb_master_model.bmp
..............\wb_master_model.v
..............\work
..............\....\spi_clgen
..............\....\.........\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\spi_shift
..............\....\.........\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\spi_slave_model
..............\....\...............\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\spi_top
..............\....\.......\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\tb_spi_top
..............\....\..........\verilog.asm
..............\....\..........\_primary.dat
..............\....\..........\_primary.vhd
..............\....\wb_master_model
..............\....\...............\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\_info
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is one of the largest source code repositories on the Internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.