Multiplier, two 0-99 multiplying the number of analog, the results displayed in the 7-segment digital tube, may FPGA platform firing ~

Final\db\add_sub_gjh.tdf
.....\..\add_sub_hjh.tdf
.....\..\add_sub_ijh.tdf
.....\..\add_sub_l8h.tdf
.....\..\add_sub_n8h.tdf
.....\..\Final.asm.qmsg
.....\..\Final.cbx.xml
.....\..\Final.cmp.cdb
.....\..\Final.cmp.hdb
.....\..\Final.cmp.kpt
.....\..\Final.cmp.logdb
.....\..\Final.cmp.rdb
.....\..\Final.cmp.tdb
.....\..\Final.cmp0.ddb
.....\..\Final.dbp
.....\..\Final.db_info
.....\..\Final.eco.cdb
.....\..\Final.eds_overflow
.....\..\Final.fit.qmsg
.....\..\Final.hier_info
.....\..\Final.hif
.....\..\Final.map.cdb
.....\..\Final.map.hdb
.....\..\Final.map.logdb
.....\..\Final.map.qmsg
.....\..\Final.pre_map.cdb
.....\..\Final.pre_map.hdb
.....\..\Final.psp
.....\..\Final.rtlv.hdb
.....\..\Final.rtlv_sg.cdb
.....\..\Final.rtlv_sg_swap.cdb
.....\..\Final.sgdiff.cdb
.....\..\Final.sgdiff.hdb
.....\..\Final.sim.hdb
.....\..\Final.sim.qmsg
.....\..\Final.sim.rdb
.....\..\Final.sim.vwf
.....\..\Final.sld_design_entry.sci
.....\..\Final.sld_design_entry_dsc.sci
.....\..\Final.syn_hier_info
.....\..\Final.tan.qmsg
.....\..\wed.zsf
.....\Final.asm.rpt
.....\Final.done
.....\Final.fit.rpt
.....\Final.fit.summary
.....\Final.flow.rpt
.....\Final.map.rpt
.....\Final.map.summary
.....\Final.pin
.....\Final.qpf
.....\Final.qsf
.....\Final.qws
.....\Final.sim.rpt
.....\Final.tan.rpt
.....\Final.tan.summary
.....\Final.vhd
.....\Final.vwf
.....\db
Final

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