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PI_Final

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.11mb
  • Downloaded :0次
  • Author :gir***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Its working and tested in Xilinx Sortware.
Packet file list
(Preview for download)
PI_Final\.lso
........\control.bgn
........\control.bit
........\Control.bld
........\Control.cmd_log
........\control.drc
........\Control.fdo
........\Control.lso
........\Control.ncd
........\Control.ngc
........\Control.ngd
........\Control.ngr
........\Control.pad
........\Control.par
........\Control.pcf
........\Control.prj
........\Control.ptwx
........\Control.spl
........\Control.stx
........\Control.sym
........\Control.syr
........\Control.tfi
........\Control.twr
........\Control.twx
........\Control.ucf
........\Control.unroutes
........\Control.ut
........\Control.xpi
........\Control.xst
........\Control_envsettings.html
........\Control_guide.ncd
........\Control_map.map
........\Control_map.mrp
........\Control_map.ncd
........\Control_map.ngm
........\Control_map.xrpt
........\Control_ngdbuild.xrpt
........\Control_pad.csv
........\Control_pad.txt
........\Control_par.xrpt
........\Control_preroute.twr
........\Control_preroute.twx
........\Control_summary.html
........\Control_summary.xml
........\Control_usage.xml
........\Control_xst.xrpt
........\impact_trial1.ipf
........\.seconfig\Control.xreport
........\.........\PI.xreport
........\.........\Trail1.projectmgr
........\.........\Trail4.projectmgr
........\.........\Trial_1.xreport
........\netgen\map\Control_map.nlf
........\......\...\control_map.sdf
........\......\...\Control_map.v
........\......\synthesis\Control_synthesis.nlf
........\......\.........\Control_synthesis.v
........\......\.........\PI_synthesis.nlf
........\......\.........\PI_synthesis.v
........\......\translate\Control_translate.nlf
........\......\.........\Control_translate.v
........\PI.cmd_log
........\PI.fdo
........\PI.lso
........\PI.ngc
........\PI.ngr
........\PI.prj
........\PI.spl
........\PI.stx
........\PI.sym
........\PI.syr
........\PI.xst
........\PID.fdo
........\PID.prj
........\PID.stx
........\PID.tfi
........\PID.xst
........\PI_envsettings.html
........\PI_Final.gise
........\PI_Final.xise
........\PI_summary.html
........\PI_xst.xrpt
........\planAhead_run_1\planAhead.jou
........\...............\planAhead.log
........\...............\planAhead_run.log
........\...............\Trail1.data\constrs_1\designprops.xml
........\...............\...........\.........\fileset.xml
........\...............\...........\.........\usercols.xml
........\...............\...........\runs\impl_1.psg
........\...............\...........\....\runs.xml
........\...............\...........\sources_1\chipscope.xml
........\...............\...........\.........\fileset.xml
........\...............\...........\.........\ports.xml
........\...............\...........\wt\webtalk_pa.xml
........\...............\Trail1.ppr
........\smartxplorer_results\.smartxplorer\.sx.debug
........\....................\.............\.sx.keepAlive.Ankit_LG_0
........\....................\.............\.sx.keepAlive.Ankit_LG_1
........\....................\.............\Ankit_LG_0.stat
........\....................\.............\Ankit_LG_1.stat
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