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simpleRAM

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 640kb
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  • Author :j*****
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Introduction - If you have any usage issues, please Google them yourself
Using several different methods of design FPFA-chip memory
Packet file list
(Preview for download)
RAM(Verilog)\db\altsyncram_8oc1.tdf
............\..\altsyncram_i741.tdf
............\..\logic_util_heursitic.dat
............\..\prev_cmp_RAM.asm.qmsg
............\..\prev_cmp_RAM.fit.qmsg
............\..\prev_cmp_RAM.map.qmsg
............\..\prev_cmp_RAM.qmsg
............\..\prev_cmp_RAM.sim.qmsg
............\..\prev_cmp_RAM.tan.qmsg
............\..\RAM.analyze_file.qmsg
............\..\RAM.asm.qmsg
............\..\RAM.asm.rdb
............\..\RAM.asm_labs.ddb
............\..\RAM.cbx.xml
............\..\RAM.cmp.bpm
............\..\RAM.cmp.cdb
............\..\RAM.cmp.ecobp
............\..\RAM.cmp.hdb
............\..\RAM.cmp.kpt
............\..\RAM.cmp.logdb
............\..\RAM.cmp.rdb
............\..\RAM.cmp.tdb
............\..\RAM.cmp0.ddb
............\..\RAM.cmp_merge.kpt
............\..\RAM.db_info
............\..\RAM.eco.cdb
............\..\RAM.eds_overflow
............\..\RAM.fit.qmsg
............\..\RAM.fnsim.hdb
............\..\RAM.fnsim.qmsg
............\..\RAM.hier_info
............\..\RAM.hif
............\..\RAM.lpc.html
............\..\RAM.lpc.rdb
............\..\RAM.lpc.txt
............\..\RAM.map.bpm
............\..\RAM.map.cdb
............\..\RAM.map.ecobp
............\..\RAM.map.hdb
............\..\RAM.map.kpt
............\..\RAM.map.logdb
............\..\RAM.map.qmsg
............\..\RAM.map_bb.cdb
............\..\RAM.map_bb.hdb
............\..\RAM.map_bb.logdb
............\..\RAM.pre_map.cdb
............\..\RAM.pre_map.hdb
............\..\RAM.rtlv.hdb
............\..\RAM.rtlv_sg.cdb
............\..\RAM.rtlv_sg_swap.cdb
............\..\RAM.sgdiff.cdb
............\..\RAM.sgdiff.hdb
............\..\RAM.sim.cvwf
............\..\RAM.sim.hdb
............\..\RAM.sim.qmsg
............\..\RAM.sim.rdb
............\..\RAM.simfam
............\..\RAM.sld_design_entry.sci
............\..\RAM.sld_design_entry_dsc.sci
............\..\RAM.smart_action.txt
............\..\RAM.syn_hier_info
............\..\RAM.tan.qmsg
............\..\RAM.tis_db_list.ddb
............\..\RAM.tmw_info
............\..\wed.wsf
............\incremental_db\compiled_partitions\RAM.root_partition.cmp.cdb
............\..............\...................\RAM.root_partition.cmp.dfp
............\..............\...................\RAM.root_partition.cmp.hdb
............\..............\...................\RAM.root_partition.cmp.kpt
............\..............\...................\RAM.root_partition.cmp.logdb
............\..............\...................\RAM.root_partition.cmp.rcfdb
............\..............\...................\RAM.root_partition.cmp.re.rcfdb
............\..............\...................\RAM.root_partition.map.cdb
............\..............\...................\RAM.root_partition.map.dpi
............\..............\...................\RAM.root_partition.map.hdb
............\..............\...................\RAM.root_partition.map.kpt
............\..............\README
............\RAM.asm.rpt
............\RAM.done
............\RAM.dpf
............\RAM.fit.rpt
............\RAM.fit.smsg
............\RAM.fit.summary
............\RAM.flow.rpt
............\RAM.map.rpt
............\RAM.map.summary
............\RAM.pin
............\RAM.pof
............\RAM.qpf
............\RAM.qsf
............\RAM.qws
............\RAM.sim.rpt
............\RAM.sof
............\RAM.tan.rpt
............\RAM.tan.summary
............\RAM.v
............\RAM.v.bak
............\RAM.vwf
....LPM)\db\altsyncram_ne81.tdf
........\..\logic_util_heursitic.dat
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