Contains the entire project is to write Verilog to achieve the function of the dual-port ram

dpram\db\logic_util_heursitic.dat
.....\..\prev_cmp_reg_dpram.qmsg
.....\..\reg_dpram.amm.cdb
.....\..\reg_dpram.asm.qmsg
.....\..\reg_dpram.asm.rdb
.....\..\reg_dpram.asm_labs.ddb
.....\..\reg_dpram.cbx.xml
.....\..\reg_dpram.cmp.bpm
.....\..\reg_dpram.cmp.cdb
.....\..\reg_dpram.cmp.hdb
.....\..\reg_dpram.cmp.kpt
.....\..\reg_dpram.cmp.logdb
.....\..\reg_dpram.cmp.rdb
.....\..\reg_dpram.cmp0.ddb
.....\..\reg_dpram.cmp1.ddb
.....\..\reg_dpram.cmp2.ddb
.....\..\reg_dpram.cmp_merge.kpt
.....\..\reg_dpram.db_info
.....\..\reg_dpram.eda.qmsg
.....\..\reg_dpram.fit.qmsg
.....\..\reg_dpram.hier_info
.....\..\reg_dpram.hif
.....\..\reg_dpram.idb.cdb
.....\..\reg_dpram.lpc.html
.....\..\reg_dpram.lpc.rdb
.....\..\reg_dpram.lpc.txt
.....\..\reg_dpram.map.bpm
.....\..\reg_dpram.map.cdb
.....\..\reg_dpram.map.hdb
.....\..\reg_dpram.map.kpt
.....\..\reg_dpram.map.logdb
.....\..\reg_dpram.map.qmsg
.....\..\reg_dpram.map_bb.cdb
.....\..\reg_dpram.map_bb.hdb
.....\..\reg_dpram.map_bb.logdb
.....\..\reg_dpram.pre_map.cdb
.....\..\reg_dpram.pre_map.hdb
.....\..\reg_dpram.rpp.qmsg
.....\..\reg_dpram.rtlv.hdb
.....\..\reg_dpram.rtlv_sg.cdb
.....\..\reg_dpram.rtlv_sg_swap.cdb
.....\..\reg_dpram.sgate.rvd
.....\..\reg_dpram.sgate_sm.rvd
.....\..\reg_dpram.sgdiff.cdb
.....\..\reg_dpram.sgdiff.hdb
.....\..\reg_dpram.sld_design_entry.sci
.....\..\reg_dpram.sld_design_entry_dsc.sci
.....\..\reg_dpram.smart_action.txt
.....\..\reg_dpram.sta.qmsg
.....\..\reg_dpram.sta.rdb
.....\..\reg_dpram.sta_cmp.8_slow.tdb
.....\..\reg_dpram.syn_hier_info
.....\..\reg_dpram.tis_db_list.ddb
.....\..\reg_dpram.tmw_info
.....\incremental_db\compiled_partitions\reg_dpram.db_info
.....\..............\...................\reg_dpram.root_partition.cmp.cbp
.....\..............\...................\reg_dpram.root_partition.cmp.cdb
.....\..............\...................\reg_dpram.root_partition.cmp.dfp
.....\..............\...................\reg_dpram.root_partition.cmp.hdb
.....\..............\...................\reg_dpram.root_partition.cmp.kpt
.....\..............\...................\reg_dpram.root_partition.cmp.logdb
.....\..............\...................\reg_dpram.root_partition.cmp.rcfdb
.....\..............\...................\reg_dpram.root_partition.cmp.re.rcfdb
.....\..............\...................\reg_dpram.root_partition.map.cbp
.....\..............\...................\reg_dpram.root_partition.map.cdb
.....\..............\...................\reg_dpram.root_partition.map.dpi
.....\..............\...................\reg_dpram.root_partition.map.hdb
.....\..............\...................\reg_dpram.root_partition.map.kpt
.....\..............\README
.....\reg_dpram.asm.rpt
.....\reg_dpram.done
.....\reg_dpram.eda.rpt
.....\reg_dpram.fit.rpt
.....\reg_dpram.fit.smsg
.....\reg_dpram.fit.summary
.....\reg_dpram.flow.rpt
.....\reg_dpram.map.rpt
.....\reg_dpram.map.summary
.....\reg_dpram.pin
.....\reg_dpram.pof
.....\reg_dpram.qpf
.....\reg_dpram.qsf
.....\reg_dpram.sof
.....\reg_dpram.sta.rpt
.....\reg_dpram.sta.summary
.....\reg_dpram.v
.....\reg_dpram.v.bak
.....\reg_dpram_nativelink_simulation.rpt
.....\simulation\modelsim\modelsim.ini
.....\..........\........\msim_transcript
.....\..........\........\reg_dpram.sft
.....\..........\........\reg_dpram.vo
.....\..........\........\reg_dpram.vt
.....\..........\........\reg_dpram.vt.bak
.....\..........\........\reg_dpram_fast.vo
.....\..........\........\reg_dpram_modelsim.xrf
.....\..........\........\reg_dpram_run_msim_rtl_verilog.do
.....\..........\........\reg_dpram_run_msim_rtl_verilog.do.bak
.....\..........\........\reg_dpram_run_msim_rtl_verilog.do.bak1
.....\..........\........\reg_dpram_run_msim_rtl_verilog.do.bak10

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