Generation and distribution of clock signals inside the VLSI systems is one of the most important problems in the design of VLSI systems. Because of the process variations and interconnect parasitics, clock signals delays vary for dierent paths. The clock signals should have zero clock skew, that is to say all the clock signals should arrive at the inputs of registers at the same time. Otherwise latches and ip-ops get clock signal at dierent time instances. In order to circuit to operate correctly these dierences should be eliminated, ideally to zero. However it is not possible practically and 10 of the clock cycle is expended in order to compensate for clock skew[1]. To handle this problem, several solutions are proposed.

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