Introduction - If you have any usage issues, please Google them yourself
The Algorithm is converted to HDL description for FPGA realization．The designs of the core Modules of demodulator, including digital down-conversion，carrier ring，bit synchronization loop design, are described in detail．And a block diagram and simulated waveforms are provide in the latter part．Also the soft-core processor technology of Altera’s NiosII is applied in the design for carrier frequency offset correction and the monitoring and control of the separate parts of demodulator．Finally, the test methods and results of key performance indicators of the IF Demodulator QPSK are given to show that the design given in this paper can reach the performance requirements expected.