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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 779kb
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  • Author :胡****
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fpga verilong
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(Preview for download)
14 adc+数码管显示\Block1.bdf
.................\db\add_sub_4ch.tdf
.................\..\add_sub_lkc.tdf
.................\..\add_sub_mkc.tdf
.................\..\add_sub_pah.tdf
.................\..\alt_u_div_e2f.tdf
.................\..\alt_u_div_u5f.tdf
.................\..\hu14.asm.qmsg
.................\..\hu14.asm_labs.ddb
.................\..\hu14.cbx.xml
.................\..\hu14.cmp.bpm
.................\..\hu14.cmp.cdb
.................\..\hu14.cmp.ecobp
.................\..\hu14.cmp.hdb
.................\..\hu14.cmp.kpt
.................\..\hu14.cmp.logdb
.................\..\hu14.cmp.rdb
.................\..\hu14.cmp.tdb
.................\..\hu14.cmp0.ddb
.................\..\hu14.cmp_merge.kpt
.................\..\hu14.db_info
.................\..\hu14.eco.cdb
.................\..\hu14.fit.qmsg
.................\..\hu14.hier_info
.................\..\hu14.hif
.................\..\hu14.lpc.html
.................\..\hu14.lpc.rdb
.................\..\hu14.lpc.txt
.................\..\hu14.map.bpm
.................\..\hu14.map.cdb
.................\..\hu14.map.ecobp
.................\..\hu14.map.hdb
.................\..\hu14.map.kpt
.................\..\hu14.map.logdb
.................\..\hu14.map.qmsg
.................\..\hu14.map_bb.cdb
.................\..\hu14.map_bb.hdb
.................\..\hu14.map_bb.logdb
.................\..\hu14.pre_map.cdb
.................\..\hu14.pre_map.hdb
.................\..\hu14.rtlv.hdb
.................\..\hu14.rtlv_sg.cdb
.................\..\hu14.rtlv_sg_swap.cdb
.................\..\hu14.sgdiff.cdb
.................\..\hu14.sgdiff.hdb
.................\..\hu14.sld_design_entry.sci
.................\..\hu14.sld_design_entry_dsc.sci
.................\..\hu14.syn_hier_info
.................\..\hu14.tan.qmsg
.................\..\hu14.tis_db_list.ddb
.................\..\hu14_global_asgn_op.abo
.................\..\lpm_divide_4gm.tdf
.................\..\lpm_divide_cem.tdf
.................\..\lpm_divide_f6m.tdf
.................\..\prev_cmp_hu14.asm.qmsg
.................\..\prev_cmp_hu14.fit.qmsg
.................\..\prev_cmp_hu14.map.qmsg
.................\..\prev_cmp_hu14.qmsg
.................\..\prev_cmp_hu14.tan.qmsg
.................\..\sign_div_unsign_enh.tdf
.................\..\sign_div_unsign_mlh.tdf
.................\hu14.asm.rpt
.................\hu14.bsf
.................\hu14.done
.................\hu14.dpf
.................\hu14.fit.rpt
.................\hu14.fit.smsg
.................\hu14.fit.summary
.................\hu14.flow.rpt
.................\hu14.map.rpt
.................\hu14.map.summary
.................\hu14.pin
.................\hu14.pof
.................\hu14.qpf
.................\hu14.qsf
.................\hu14.qws
.................\hu14.sof
.................\hu14.tan.rpt
.................\hu14.tan.summary
.................\hu14.v
.................\hu14.v.bak
.................\incremental_db\compiled_partitions\hu14.root_partition.cmp.atm
.................\..............\...................\hu14.root_partition.cmp.dfp
.................\..............\...................\hu14.root_partition.cmp.hdbx
.................\..............\...................\hu14.root_partition.cmp.kpt
.................\..............\...................\hu14.root_partition.cmp.logdb
.................\..............\...................\hu14.root_partition.cmp.rcf
.................\..............\...................\hu14.root_partition.map.atm
.................\..............\...................\hu14.root_partition.map.dpi
.................\..............\...................\hu14.root_partition.map.hdbx
.................\..............\...................\hu14.root_partition.map.kpt
.................\..............\README
.................\serv_req_info.txt
.................\shumaguan.bsf
.................\shumaguan.v
.................\shumaguan.v.bak
.................\Verilog1.v
.................\Verilog1.v.bak
.................\incremental_db\compiled_partitions
.................\db
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