implementation of multi channel uart

ACTUAL CODE\baud_gen.v
...........\baud_gen_tb.v
...........\Controller_1.v
...........\Controller_1_tb.v
...........\Dmux12.v
...........\Dmux12_tb.v
...........\Dmux14.v
...........\Dmux22.v
...........\fifo11.v
...........\fifomem.v
...........\fifomem1.v
...........\fifomem_tb.v
...........\mult_top.v
...........\mult_top1.v
...........\mult_top_tb.v
...........\Mux21.v
...........\Mux21_tb.v
...........\Mux22.v
...........\Mux41.v
...........\Mux_con.v
...........\parity_gen.v
...........\parity_gen_tb.v
...........\reg_block.v
...........\reg_block1.v
...........\reg_block_tb.v
...........\rptr_empty.v
...........\rptr_empty1.v
...........\rptr_empty_tb.v
...........\rx_state.v
...........\rx_state_tb.v
...........\sync1_r2w.v
...........\sync1_w2r.v
...........\sync_r2w.v
...........\sync_r2w_tb.v
...........\sync_w2r.v
...........\sync_w2r_tb.v
...........\transbuf.v
...........\transbuf_tb.v
...........\tx_state.v
...........\tx_state_tb.v
...........\uart_top1.v
...........\uart_top1_tb.v
...........\wptr_full.v
...........\wptr_full1.v
...........\wptr_full_tb.v
ACTUAL CODE

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