the Verilog FPGA060 experiments and documentation of the encoder

encode\designer\impl1\designer.log
......\........\.....\my_encode.adb
......\........\.....\my_encode.dat
......\........\.....\...........tf\verify.log
......\........\.....\my_encode.ide_des
......\........\.....\my_encode.pdb
......\........\.....\my_encode.pdb.depends
......\........\.....\my_encode.tcl
......\encode.prj
......\hdl\my_encode.v
......\simulation\modelsim.ini
......\.martgen\smartgen.aws
......\.ynthesis\my_encode.areasrr
......\.........\my_encode.edn
......\.........\my_encode.fse
......\.........\my_encode.htm
......\.........\my_encode.map
......\.........\my_encode.pdc
......\.........\my_encode.sap
......\.........\my_encode.sdf
......\.........\my_encode.so
......\.........\my_encode.srd
......\.........\my_encode.srm
......\.........\my_encode.srr
......\.........\my_encode.srs
......\.........\my_encode.szr
......\.........\my_encode.tlg
......\.........\my_encode_sdc.sdc
......\.........\my_encode_syn.prj
......\.........\run_options.txt
......\.........\stdout.log
......\.........\.yntmp\my_encode.plg
......\.........\......\my_encode_flink.htm
......\.........\......\my_encode_srr.htm
......\.........\......\my_encode_toc.htm
......\.........\......\sap.log
......\viewdraw\vf\project.lst
......\........\viewdraw.ini
......\designer\impl1\my_encode.dtf
......\........\.....\simulation
......\........\impl1
......\synthesis\backup
......\.........\coreip
......\.........\syntmp
......\viewdraw\sch
......\........\sym
......\........\vf
......\........\wir
......\component
......\constraint
......\coreconsole
......\designer
......\hdl
......\phy_synthesis
......\simulation
......\smartgen
......\stimulus
......\synthesis
......\viewdraw
encode

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