Experimental routines and documentation of the NAND gate

my_nand\component\work\my_nand\my_nand.cxf
.......\.........\....\.......\my_nand.sdb
.......\designer\impl1\designer.log
.......\........\.....\my_nand.adb
.......\........\.....\my_nand.dat
.......\........\.....\.........tf\verify.log
.......\........\.....\my_nand.ide_des
.......\........\.....\my_nand.pdb
.......\........\.....\my_nand.pdb.depends
.......\........\.....\my_nand.tcl
.......\hdl\my_anad.v
.......\my_nand.prj
.......\simulation\modelsim.ini
.......\.martgen\my_nand_work.ixf
.......\........\smartgen.aws
.......\.ynthesis\my_nand.areasrr
.......\.........\my_nand.edn
.......\.........\my_nand.map
.......\.........\my_nand.pdc
.......\.........\my_nand.sdf
.......\.........\my_nand.so
.......\.........\my_nand.srd
.......\.........\my_nand.srm
.......\.........\my_nand.srr
.......\.........\my_nand.srs
.......\.........\my_nand.szr
.......\.........\my_nand.tlg
.......\.........\my_nand_sdc.sdc
.......\.........\my_nand_syn.prj
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\.yntmp\my_nand.plg
.......\viewdraw\vf\project.lst
.......\........\viewdraw.ini
.......\component\work\my_nand
.......\designer\impl1\my_nand.dtf
.......\........\.....\simulation
.......\component\work
.......\designer\impl1
.......\synthesis\backup
.......\.........\coreip
.......\.........\syntmp
.......\viewdraw\sch
.......\........\sym
.......\........\vf
.......\........\wir
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\hdl
.......\phy_synthesis
.......\simulation
.......\smartgen
.......\stimulus
.......\synthesis
.......\viewdraw
my_nand

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