The DSP Builder-based fir filter, and on the simulation project file in Modelsim is doing FPGA-based fir filter part of the

FIR_32tap.ipx
FIR_32tap.mdl
FIR_32tap.mdlxml
FIR_32tap.qip
FIR_32tap_add.tcl
FIR_32tap_dspbuilder
....................\db
....................\..\add_sub_8hk.tdf
....................\..\add_sub_fph.tdf
....................\..\alt_dspbuilder_AROUND.vhd
....................\..\alt_dspbuilder_ASAT.vhd
....................\..\alt_dspbuilder_cast.jvgen_cache.xml
....................\..\alt_dspbuilder_cast.vhd
....................\..\alt_dspbuilder_cast_GN5MS43UAC.vhd
....................\..\alt_dspbuilder_cast_GNVJUWW4S2.vhd
....................\..\alt_dspbuilder_cast_GNY664AYAX.vhd
....................\..\alt_dspbuilder_cast_GNZMVZUTZC.vhd
....................\..\alt_dspbuilder_clock.jvgen_cache.xml
....................\..\alt_dspbuilder_clock.vhd
....................\..\alt_dspbuilder_clock_GNDZSP37O7.vhd
....................\..\alt_dspbuilder_clock_GNU4YM7HGX.vhd
....................\..\alt_dspbuilder_delay.jvgen_cache.xml
....................\..\alt_dspbuilder_delay.vhd
....................\..\alt_dspbuilder_delay_GNNDUYVBEV.vhd
....................\..\alt_dspbuilder_logical_bit_op.jvgen_cache.xml
....................\..\alt_dspbuilder_logical_bit_op.vhd
....................\..\alt_dspbuilder_logical_bit_op_GNA5ZFEL7V.vhd
....................\..\alt_dspbuilder_parallel_adder.jvgen_cache.xml
....................\..\alt_dspbuilder_parallel_adder.vhd
....................\..\alt_dspbuilder_parallel_adder_GNWW7WOSZY.vhd
....................\..\alt_dspbuilder_parallel_add_db.vhd
....................\..\alt_dspbuilder_pipelined_adder.jvgen_cache.xml
....................\..\alt_dspbuilder_pipelined_adder.vhd
....................\..\alt_dspbuilder_pipelined_adder_GNAMNIVCS7.vhd
....................\..\alt_dspbuilder_port.jvgen_cache.xml
....................\..\alt_dspbuilder_port.vhd
....................\..\alt_dspbuilder_port_GN22JXT7RG.vhd
....................\..\alt_dspbuilder_port_GN2YWA34YW.vhd
....................\..\alt_dspbuilder_port_GNAMDQJW2W.vhd
....................\..\alt_dspbuilder_port_GNATH6VNYA.vhd
....................\..\alt_dspbuilder_port_GNDG36S3B7.vhd
....................\..\alt_dspbuilder_port_GNDRMZVU7K.vhd
....................\..\alt_dspbuilder_port_GNENK2BWIL.vhd
....................\..\alt_dspbuilder_port_GNTCBH5HXI.vhd
....................\..\alt_dspbuilder_port_GNTPNWV3ZD.vhd
....................\..\alt_dspbuilder_port_GNXKDILRL2.vhd
....................\..\alt_dspbuilder_SAdderSub.vhd
....................\..\alt_dspbuilder_sAltrBitPropagate.vhd
....................\..\alt_dspbuilder_sAltrPropagate.vhd
....................\..\alt_dspbuilder_SBF.vhd
....................\..\alt_dspbuilder_SBitLogical.vhd
....................\..\alt_dspbuilder_sDAMultAddAltr.vhd
....................\..\alt_dspbuilder_SDelay.vhd
....................\..\alt_dspbuilder_shifttaps.jvgen_cache.xml
....................\..\alt_dspbuilder_shifttaps.vhd
....................\..\alt_dspbuilder_shifttaps_GN2ZZ46R4K.vhd
....................\..\alt_dspbuilder_SInitDelay.vhd
....................\..\alt_dspbuilder_sLpmAddSub.vhd
....................\..\alt_dspbuilder_sMultiBitAddSub.vhd
....................\..\alt_dspbuilder_SShiftTap.vhd
....................\..\alt_dspbuilder_sum_of_products.jvgen_cache.xml
....................\..\alt_dspbuilder_sum_of_products.vhd
....................\..\alt_dspbuilder_sum_of_products_GNBZHTJUHL.vhd
....................\..\alt_dspbuilder_sum_of_products_GNXT7IOIYO.vhd
....................\..\alt_dspbuilder_testbench_capture.jvgen_cache.xml
....................\..\alt_dspbuilder_testbench_capture.vhd
....................\..\alt_dspbuilder_testbench_capture_GN4DENKN6W.vhd
....................\..\alt_dspbuilder_testbench_capture_GNPSTB4R6K.vhd
....................\..\alt_dspbuilder_testbench_capture_GNTFBLHI44.vhd
....................\..\alt_dspbuilder_testbench_clock.jvgen_cache.xml
....................\..\alt_dspbuilder_testbench_clock.vhd
....................\..\alt_dspbuilder_testbench_clock_GNLZZKBM2J.vhd
....................\..\alt_dspbuilder_testbench_salt.jvgen_cache.xml
....................\..\alt

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