Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.

32bit RISC CPU IP\potato_verilog\alu.v
.................\..............\cntrl_rf.v
.................\..............\cpu.v
.................\..............\decode.v
.................\..............\forward.v
.................\..............\interrupt.v
.................\..............\mpu.v
.................\..............\pc_gen.v
.................\..............\ram.v
.................\..............\regfile.v
.................\..............\reg_ex.v
.................\..............\reg_id.v
.................\..............\reg_if.v
.................\..............\reg_mem.v
.................\..............\rom.v
.................\..............\write_back.v
.................\约束文件.doc
.................\potato_verilog
32bit RISC CPU IP

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