Verilog fpga VGA port Quartus

ex16_sd_vga_photo\sdram_mdl0822\PLL_ctrl.bsf
.................\.............\PLL_ctrl.ppf
.................\.............\PLL_ctrl.qip
.................\.............\PLL_ctrl.v
.................\.............\PLL_ctrl_bb.v
.................\.............\PLL_ctrl_inst.v
.................\.............\PLL_ctrl_wave0.jpg
.................\.............\PLL_ctrl_waveforms.html
.................\.............\rdfifo.bsf
.................\.............\rdfifo.qip
.................\.............\rdfifo.v
.................\.............\rdfifo_bb.v
.................\.............\rdfifo_inst.v
.................\.............\rdfifo_wave0.jpg
.................\.............\rdfifo_waveforms.html
.................\.............\rgb_ram.bsf
.................\.............\rgb_ram.qip
.................\.............\rgb_ram.v
.................\.............\rgb_ram_bb.v
.................\.............\rgb_ram_inst.v
.................\.............\rgb_ram_wave0.jpg
.................\.............\rgb_ram_wave1.jpg
.................\.............\rgb_ram_waveforms.html
.................\.............\sdcard_ctrl.v
.................\.............\sdfifo_ctrl.v
.................\.............\sdram_cmd.v
.................\.............\sdram_ctrl.v
.................\.............\sdram_top.v
.................\.............\sdram_wr_data.v
.................\.............\sdrsvgaprj.v
.................\.............\sdr_para.v
.................\.............\sdr_test.done
.................\.............\sdr_test.dpf
.................\.............\sdr_test.fit.smsg
.................\.............\sdr_test.fit.summary
.................\.............\sdr_test.map.summary
.................\.............\sdr_test.pin
.................\.............\sdr_test.pof
.................\.............\sdr_test.qpf
.................\.............\sdr_test.qsf
.................\.............\sdr_test.qws
.................\.............\sdr_test.rar
.................\.............\sdr_test.sdc
.................\.............\sdr_test.sof
.................\.............\sdr_test.sta.summary
.................\.............\sdr_test.v
.................\.............\sdr_test_assignment_defaults.qdf
.................\.............\sd_ctrl.v
.................\.............\spi_ctrl.v
.................\.............\sys_ctrl.v
.................\.............\uart_ctrl.v
.................\.............\uart_speed_select.v
.................\.............\uart_tx.v
.................\.............\UNUSED
.................\.............\vga_ctrl.v
.................\.............\wrfifo.bsf
.................\.............\wrfifo.qip
.................\.............\wrfifo.v
.................\.............\wrfifo_bb.v
.................\.............\wrfifo_inst.v
.................\.............\wrfifo_wave0.jpg
.................\.............\wrfifo_waveforms.html
.................\.............\时序分析.txt
.................\sdram_mdl0822
ex16_sd_vga_photo

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