The digital electric clock with VHDL, with alarm function

数字电子钟程序\Block1.bdf
..............\clk.qsf
..............\clk.qws
..............\db\add_sub_4ph.tdf
..............\..\add_sub_m9c.tdf
..............\..\add_sub_n9c.tdf
..............\..\add_sub_o5c.tdf
..............\..\add_sub_o9c.tdf
..............\..\add_sub_onh.tdf
..............\..\add_sub_p5c.tdf
..............\..\add_sub_p9c.tdf
..............\..\add_sub_pnh.tdf
..............\..\add_sub_q5c.tdf
..............\..\add_sub_q9c.tdf
..............\..\add_sub_qnh.tdf
..............\..\add_sub_r9c.tdf
..............\..\alt_u_div_fke.tdf
..............\..\alt_u_div_hke.tdf
..............\..\alt_u_div_ike.tdf
..............\..\alt_u_div_lke.tdf
..............\..\alt_u_div_nke.tdf
..............\..\alt_u_div_pke.tdf
..............\..\alt_u_div_qke.tdf
..............\..\alt_u_div_tke.tdf
..............\..\clk.db_info
..............\..\clk.eco.cdb
..............\..\clk.sld_design_entry.sci
..............\..\fenwei.asm.qmsg
..............\..\fenwei.cbx.xml
..............\..\fenwei.cmp.cdb
..............\..\fenwei.cmp.hdb
..............\..\fenwei.cmp.logdb
..............\..\fenwei.cmp.rdb
..............\..\fenwei.cmp.tdb
..............\..\fenwei.cmp0.ddb
..............\..\fenwei.dbp
..............\..\fenwei.db_info
..............\..\fenwei.eco.cdb
..............\..\fenwei.eds_overflow
..............\..\fenwei.fit.qmsg
..............\..\fenwei.hier_info
..............\..\fenwei.hif
..............\..\fenwei.map.cdb
..............\..\fenwei.map.hdb
..............\..\fenwei.map.logdb
..............\..\fenwei.map.qmsg
..............\..\fenwei.pre_map.cdb
..............\..\fenwei.pre_map.hdb
..............\..\fenwei.psp
..............\..\fenwei.rtlv.hdb
..............\..\fenwei.rtlv_sg.cdb
..............\..\fenwei.rtlv_sg_swap.cdb
..............\..\fenwei.sgdiff.cdb
..............\..\fenwei.sgdiff.hdb
..............\..\fenwei.sim.hdb
..............\..\fenwei.sim.qmsg
..............\..\fenwei.sim.rdb
..............\..\fenwei.sim.vwf
..............\..\fenwei.sld_design_entry.sci
..............\..\fenwei.sld_design_entry_dsc.sci
..............\..\fenwei.smp_dump.txt
..............\..\fenwei.syn_hier_info
..............\..\fenwei.tan.qmsg
..............\..\lpm_divide_1ql.tdf
..............\..\lpm_divide_32m.tdf
..............\..\lpm_divide_42m.tdf
..............\..\lpm_divide_7ql.tdf
..............\..\lpm_divide_9ql.tdf
..............\..\lpm_divide_r1m.tdf
..............\..\lpm_divide_s1m.tdf
..............\..\lpm_divide_vpl.tdf
..............\..\sign_div_unsign_4kh.tdf
..............\..\sign_div_unsign_5kh.tdf
..............\..\sign_div_unsign_6kh.tdf
..............\..\sign_div_unsign_7kh.tdf
..............\..\sign_div_unsign_ckh.tdf
..............\..\sign_div_unsign_dkh.tdf
..............\..\sign_div_unsign_ekh.tdf
..............\..\sign_div_unsign_fkh.tdf
..............\..\wed.zsf
..............\digitalclock.bsf
..............\digitalclock.vhd
..............\Disp.bsf
..............\Disp.vhd
..............\disp_scan.bsf
..............\disp_scan.vhd
..............\disp_scan.vwf
..............\fenwei.asm.rpt
..............\fenwei.cdf
..............\fenwei.done
..............\fenwei.dpf
..............\fenwei.fit.rpt
..............\fenwei.fit.summary
..............\fenwei.flow.rpt
..............\fenwei.map.rpt
..............\fenwei.map.summary
..............\fenwei.pin
..............\fenwei.pof
..............\fenwei.qpf
..............\fenwei.qsf

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