Written in Verilog HDL using the FPGA control procedures AD0809

ad_0809\ad_0809.qpf
.......\ad_0809.qsf
.......\ad_0809.v
.......\ad_0809.qws
.......\db\ad_0809.db_info
.......\..\ad_0809.fit.qmsg
.......\..\ad_0809.sim.qmsg
.......\..\ad_0809.map.qmsg
.......\..\ad_0809.cmp.logdb
.......\..\ad_0809.rtlv.hdb
.......\..\wed.zsf
.......\..\ad_0809.cbx.xml
.......\..\ad_0809.rtlv_sg_swap.cdb
.......\..\ad_0809.pre_map.cdb
.......\..\ad_0809.pre_map.hdb
.......\..\ad_0809.rtlv_sg.cdb
.......\..\ad_0809.smp_dump.txt
.......\..\ad_0809.map.logdb
.......\..\ad_0809.sgdiff.hdb
.......\..\ad_0809.map.cdb
.......\..\ad_0809.map.hdb
.......\..\ad_0809.signalprobe.cdb
.......\..\ad_0809.cmp.tdb
.......\..\ad_0809.asm.qmsg
.......\..\ad_0809.sgdiff.cdb
.......\..\ad_0809.sld_design_entry_dsc.sci
.......\..\ad_0809.tan.qmsg
.......\..\ad_0809.cmp.hdb
.......\..\ad_0809.sim.hdb
.......\..\ad_0809.asm_labs.ddb
.......\..\ad_0809.cmp.rdb
.......\..\ad_0809.cmp0.ddb
.......\..\ad_0809.cmp.cdb
.......\..\ad_0809.sim.vwf
.......\..\ad_0809.eds_overflow
.......\..\ad_0809.sim.rdb
.......\..\ad_0809.sld_design_entry.sci
.......\..\ad_0809.eco.cdb
.......\..\ad_0809.hif
.......\..\ad_0809.hier_info
.......\..\ad_0809.psp
.......\..\ad_0809.dbp
.......\..\ad_0809.syn_hier_info
.......\..\ad_0809.cmp.kpt
.......\ad_0809.map.rpt
.......\ad_0809.flow.rpt
.......\ad_0809.map.summary
.......\ad_0809.pin
.......\ad_0809.fit.rpt
.......\ad_0809.fit.smsg
.......\ad_0809.fit.summary
.......\ad_0809.pof
.......\ad_0809.asm.rpt
.......\ad_0809.tan.summary
.......\ad_0809.tan.rpt
.......\ad_0809.done
.......\ad_0809.vwf
.......\ad_0809.sim.rpt
.......\db
ad_0809

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