PCI Target

RD1008\docs
......\....\rd1008.pdf
......\....\rd1008_readme.txt
......\project
......\.......\pci.lct
......\.......\pci_tb_vhd.udo_example
......\.......\pci_verilog.lpf
......\.......\pci_vhdl.lpf
......\simulation
......\..........\verilog
......\..........\.......\rtl_verilog.do
......\..........\.......\timing_verilog.do
......\..........\vhdl
......\..........\....\rtl_vhdl.do
......\..........\....\timing_vhdl.do
......\source
......\......\verilog
......\......\.......\base_addr_chk.v
......\......\.......\config_mux.v
......\......\.......\glue.v
......\......\.......\pargen.v
......\......\.......\pci_top.v
......\......\.......\retry_count.v
......\......\.......\state_machine.v
......\......\vhdl
......\......\....\base_addr_chk.vhd
......\......\....\config_mux.vhd
......\......\....\glue.vhd
......\......\....\pargen.vhd
......\......\....\pargen.vhd.bak
......\......\....\pci_top.vhd
......\......\....\retry_count.vhd
......\......\....\state_machine.vhd
......\testbench
......\.........\verilog
......\.........\.......\bkend_daemon.v
......\.........\.......\pci_clk_reset.v
......\.........\.......\pci_stim.v
......\.........\.......\pci_tb.v
......\.........\.......\tasks.v
......\.........\verilog_for_classic
......\.........\...................\pci_tb.v
......\.........\vhdl
......\.........\....\bkend_daemon.vhd
......\.........\....\lattice_lib.vhd
......\.........\....\pci_clk_reset.vhd
......\.........\....\pci_stim.vhd
......\.........\....\pci_tb.vhd
......\.........\vhdl_for_classic
......\.........\................\pci_tb.vhd
RD1008

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