Verilog language with digital display test program. By dividing the clock count to make the digital control to 640ms intervals from 1 to F. This package also contains a compressed digital display test program modelsim simulation files.

4----数码管显示
...............\#####数码管#####
...............\db
...............\..\prev_cmp_shumaguan.map.qmsg
...............\..\prev_cmp_shumaguan.qmsg
...............\..\shumaguan.cbx.xml
...............\..\shumaguan.cmp.rdb
...............\..\shumaguan.db_info
...............\..\shumaguan.eco.cdb
...............\..\shumaguan.hier_info
...............\..\shumaguan.hif
...............\..\shumaguan.map.cdb
...............\..\shumaguan.map.hdb
...............\..\shumaguan.map.logdb
...............\..\shumaguan.map.qmsg
...............\..\shumaguan.pre_map.cdb
...............\..\shumaguan.pre_map.hdb
...............\..\shumaguan.rtlv.hdb
...............\..\shumaguan.rtlv_sg.cdb
...............\..\shumaguan.rtlv_sg_swap.cdb
...............\..\shumaguan.sgdiff.cdb
...............\..\shumaguan.sgdiff.hdb
...............\..\shumaguan.sld_design_entry.sci
...............\..\shumaguan.sld_design_entry_dsc.sci
...............\..\shumaguan.syn_hier_info
...............\..\shumaguan.tis_db_list.ddb
...............\..\shumaguan.tmw_info
...............\shumaguan.done
...............\shumaguan.flow.rpt
...............\shumaguan.map.rpt
...............\shumaguan.map.summary
...............\shumaguan.qpf
...............\shumaguan.qsf
...............\shumaguan.qws
...............\shumaguan.v
...............\shumaguan.v.bak

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