Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D flip-flop behavior, synchronous counters, asynchronous counters

verilog1\4位二进制数的乘法器\counter.v
........\...................\cou_16.asm.rpt
........\...................\cou_16.done
........\...................\cou_16.dpf
........\...................\cou_16.fit.rpt
........\...................\cou_16.fit.smsg
........\...................\cou_16.fit.summary
........\...................\cou_16.flow.rpt
........\...................\cou_16.map.rpt
........\...................\cou_16.map.summary
........\...................\cou_16.pin
........\...................\cou_16.pof
........\...................\cou_16.qpf
........\...................\cou_16.qsf
........\...................\cou_16.qws
........\...................\cou_16.sim.rpt
........\...................\cou_16.sof
........\...................\cou_16.tan.rpt
........\...................\cou_16.tan.summary
........\...................\cou_16.v
........\...................\cou_16.vwf
........\...................\db\cou_16.asm.qmsg
........\...................\..\cou_16.cbx.xml
........\...................\..\cou_16.cmp.cdb
........\...................\..\cou_16.cmp.hdb
........\...................\..\cou_16.cmp.kpt
........\...................\..\cou_16.cmp.logdb
........\...................\..\cou_16.cmp.rdb
........\...................\..\cou_16.cmp.tdb
........\...................\..\cou_16.cmp0.ddb
........\...................\..\cou_16.dbp
........\...................\..\cou_16.db_info
........\...................\..\cou_16.eco.cdb
........\...................\..\cou_16.eds_overflow
........\...................\..\cou_16.fit.qmsg
........\...................\..\cou_16.hier_info
........\...................\..\cou_16.hif
........\...................\..\cou_16.map.cdb
........\...................\..\cou_16.map.hdb
........\...................\..\cou_16.map.logdb
........\...................\..\cou_16.map.qmsg
........\...................\..\cou_16.pre_map.cdb
........\...................\..\cou_16.pre_map.hdb
........\...................\..\cou_16.psp
........\...................\..\cou_16.rtlv.hdb
........\...................\..\cou_16.rtlv_sg.cdb
........\...................\..\cou_16.rtlv_sg_swap.cdb
........\...................\..\cou_16.sgdiff.cdb
........\...................\..\cou_16.sgdiff.hdb
........\...................\..\cou_16.signalprobe.cdb
........\...................\..\cou_16.sim.hdb
........\...................\..\cou_16.sim.qmsg
........\...................\..\cou_16.sim.rdb
........\...................\..\cou_16.sim.vwf
........\...................\..\cou_16.sld_design_entry.sci
........\...................\..\cou_16.sld_design_entry_dsc.sci
........\...................\..\cou_16.syn_hier_info
........\...................\..\cou_16.tan.qmsg
........\...................\..\wed.zsf
........\5分频器\cmp_state.ini
........\.......\counter.v
........\.......\db\div.asm.qmsg
........\.......\..\div.cbx.xml
........\.......\..\div.cmp.cdb
........\.......\..\div.cmp.hdb
........\.......\..\div.cmp.kpt
........\.......\..\div.cmp.logdb
........\.......\..\div.cmp.rdb
........\.......\..\div.cmp.tdb
........\.......\..\div.cmp0.ddb
........\.......\..\div.dbp
........\.......\..\div.db_info
........\.......\..\div.eco.cdb
........\.......\..\div.eds_overflow
........\.......\..\div.fit.qmsg
........\.......\..\div.hier_info
........\.......\..\div.hif
........\.......\..\div.map.cdb
........\.......\..\div.map.hdb
........\.......\..\div.map.logdb
........\.......\..\div.map.qmsg
........\.......\..\div.pre_map.cdb
........\.......\..\div.pre_map.hdb
........\.......\..\div.psp
........\.......\..\div.rtlv.hdb
........\.......\..\div.rtlv_sg.cdb
........\.......\..\div.rtlv_sg_swap.cdb
........\.......\..\div.sgdiff.cdb
........\.......\..\div.sgdiff.hdb
........\.......\..\div.signalprobe.cdb
........\.......\..\div.sim.hdb
........\.......\..\div.sim.qmsg
........\.......\..\div.sim.rdb
........\.......\..\div.sim.vwf
........\.......\..\div.sld_design_entry.sci
........\.......\..\div.sld_design_entry_dsc.sci
........\.......\..\div.syn_hier_info
........\.......\..\div.tan.qmsg
........\.......\..\div_cmp.q

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