Introduction - If you have any usage issues, please Google them yourself
*Project Name :debounce
*Module Name :debounce
*Target Device :Any Altera FPGA/CPLD Device
*Clkin : 50MHz
*Desisgner : zhaibin
*Date : 2011-11-18
*Version : 2.00
*Descriprion :debounce_VerilogHDL