spi bus code, written using verilog, verification by

spi\RTL.rar
...\spiMaster.v
...\spiMaster_defines.v
...\spiMasterWishBoneBI.v
...\spiTxRxData.v
...\timescale.v
...\ctrlStsRegBI.v
...\initSD.v
...\readWriteSDBlock.v
...\readWriteSPIWireData.v
...\sendCmd.v
...\sm_dpMem_dc.v
...\sm_fifoRTL.v
...\sm_RxFifo.v
...\sm_RxFifoBI.v
...\sm_TxFifo.v
...\sm_TxFifoBI.v
...\spiCtrl.v
spi

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