This instance is used to control the development board to complete the above SDRAM read and write capabilities first SDRAM write data inside, and then compare the data read out, if you do not match on the adoption of LED lights show, if consistent, LED is not lit.

SDRAM_R&W\doc\micron_sdram.pdf
.........\part1\part1_32\model\mt48lc2m32b2.v
.........\.....\........\rtl\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\sim\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\mt48lc2m32b2.v
.........\.....\........\...\Params.v
.........\.....\........\...\sd32try.cr.mti
.........\.....\........\...\sd32try.mpf
.........\.....\........\...\sdram_test_tb.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\...\sdtry.cr.mti
.........\.....\........\...\vsim.wlf
.........\.....\........\...\wave.do
.........\.....\........\...\.ork\command\verilog.asm
.........\.....\........\...\....\.......\_primary.dat
.........\.....\........\...\....\.......\_primary.vhd
.........\.....\........\...\....\..ntrol_interface\verilog.asm
.........\.....\........\...\....\.................\_primary.dat
.........\.....\........\...\....\.................\_primary.vhd
.........\.....\........\...\....\mt48lc2m32b2\verilog.asm
.........\.....\........\...\....\............\_primary.dat
.........\.....\........\...\....\............\_primary.vhd
.........\.....\........\...\....\sdram_test_tb\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\..._data_path\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\....sdram\verilog.asm
.........\.....\........\...\....\.........\_primary.dat
.........\.....\........\...\....\.........\_primary.vhd
.........\.....\........\...\....\_info
.........\.....\........\test_bench\sdram_test_tb.v
.........\.....\........\wave\32wave.bmp
.........\.....\....2_16\model\mt48lc8m16a2.v
.........\.....\........\rtl\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\sim\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\mt48lc8m16a2.v
.........\.....\........\...\mt48lc8m16a2.v.bak
.........\.....\........\...\Params.v
.........\.....\........\...\Params.v.bak
.........\.....\........\...\sdram_test_tb.v
.........\.....\........\...\sdram_test_tb.v.bak
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\...\sdr_sdram.v.bak
.........\.....\........\...\sdtest.cr.mti
.........\.....\........\...\sdtest.mpf
.........\.....\........\...\vish_stacktrace.vstf
.........\.....\........\...\vsim.wlf
.........\.....\........\...\work\command\verilog.asm
.........\.....\........\...\....\.......\_primary.dat
.........\.....\........\...\....\.......\_primary.vhd
.........\.....\........\...\....\..ntrol_interface\verilog.asm
.........\.....\........\...\....\.................\_primary.dat
.........\.....\........\...\....\.................\_primary.vhd
.........\.....\........\...\....\mt48lc8m16a2\verilog.asm
.........\.....\........\...\....\............\_primary.dat
.........\.....\........\...\....\............\_primary.vhd
.........\.....\........\...\....\sdram_test\verilog.asm
.........\.....\........\...\....\..........\_primary.dat
.........\.....\........\...\....\..........\_primary.vhd
.........\.....\........\...\....\.........._tb\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\..._data_path\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\....sdram\verilog.asm
.........\.....\........\...\....\.........\_primary.dat

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