Language Design with VHDL and verylog a 8-to-one data selector, you can simulate in the Quartus

exp1.5_mux8_1\mux8_1.qsf
.............\Project\Block1.bdf
.............\.......\db\mux8_1.asm.qmsg
.............\.......\..\mux8_1.asm_labs.ddb
.............\.......\..\mux8_1.cbx.xml
.............\.......\..\mux8_1.cmp.bpm
.............\.......\..\mux8_1.cmp.cdb
.............\.......\..\mux8_1.cmp.ecobp
.............\.......\..\mux8_1.cmp.hdb
.............\.......\..\mux8_1.cmp.logdb
.............\.......\..\mux8_1.cmp.rdb
.............\.......\..\mux8_1.cmp.tdb
.............\.......\..\mux8_1.cmp0.ddb
.............\.......\..\mux8_1.cmp2.ddb
.............\.......\..\mux8_1.db_info
.............\.......\..\mux8_1.eco.cdb
.............\.......\..\mux8_1.eds_overflow
.............\.......\..\mux8_1.fit.qmsg
.............\.......\..\mux8_1.fnsim.hdb
.............\.......\..\mux8_1.fnsim.qmsg
.............\.......\..\mux8_1.hier_info
.............\.......\..\mux8_1.hif
.............\.......\..\mux8_1.map.bpm
.............\.......\..\mux8_1.map.cdb
.............\.......\..\mux8_1.map.ecobp
.............\.......\..\mux8_1.map.hdb
.............\.......\..\mux8_1.map.logdb
.............\.......\..\mux8_1.map.qmsg
.............\.......\..\mux8_1.map_bb.cdb
.............\.......\..\mux8_1.map_bb.hdb
.............\.......\..\mux8_1.map_bb.hdbx
.............\.......\..\mux8_1.map_bb.logdb
.............\.......\..\mux8_1.pre_map.cdb
.............\.......\..\mux8_1.pre_map.hdb
.............\.......\..\mux8_1.psp
.............\.......\..\mux8_1.root_partition.cmp.atm
.............\.......\..\mux8_1.root_partition.cmp.dfp
.............\.......\..\mux8_1.root_partition.cmp.hdbx
.............\.......\..\mux8_1.root_partition.cmp.logdb
.............\.......\..\mux8_1.root_partition.cmp.rcf
.............\.......\..\mux8_1.root_partition.map.atm
.............\.......\..\mux8_1.root_partition.map.hdbx
.............\.......\..\mux8_1.root_partition.map.info
.............\.......\..\mux8_1.rtlv.hdb
.............\.......\..\mux8_1.rtlv_sg.cdb
.............\.......\..\mux8_1.rtlv_sg_swap.cdb
.............\.......\..\mux8_1.sgdiff.cdb
.............\.......\..\mux8_1.sgdiff.hdb
.............\.......\..\mux8_1.signalprobe.cdb
.............\.......\..\mux8_1.sim.cvwf
.............\.......\..\mux8_1.sim.hdb
.............\.......\..\mux8_1.sim.qmsg
.............\.......\..\mux8_1.sim.rdb
.............\.......\..\mux8_1.simfam
.............\.......\..\mux8_1.sld_design_entry.sci
.............\.......\..\mux8_1.sld_design_entry_dsc.sci
.............\.......\..\mux8_1.syn_hier_info
.............\.......\..\mux8_1.tan.qmsg
.............\.......\..\mux8_1.tis_db_list.ddb
.............\.......\..\mux8_1.tmw_info
.............\.......\..\mux_3nc.tdf
.............\.......\..\prev_cmp_mux8_1.asm.qmsg
.............\.......\..\prev_cmp_mux8_1.fit.qmsg
.............\.......\..\prev_cmp_mux8_1.map.qmsg
.............\.......\..\prev_cmp_mux8_1.qmsg
.............\.......\..\prev_cmp_mux8_1.tan.qmsg
.............\.......\..\wed.wsf
.............\.......\mux8_1.asm.rpt
.............\.......\mux8_1.bsf
.............\.......\mux8_1.done
.............\.......\mux8_1.dpf
.............\.......\mux8_1.fit.rpt
.............\.......\mux8_1.fit.smsg
.............\.......\mux8_1.fit.summary
.............\.......\mux8_1.flow.rpt
.............\.......\mux8_1.map.rpt
.............\.......\mux8_1.map.summary
.............\.......\mux8_1.pin
.............\.......\mux8_1.pof
.............\.......\mux8_1.qpf
.............\.......\mux8_1.qsf
.............\.......\mux8_1.qws
.............\.......\mux8_1.sim.rpt
.............\.......\mux8_1.sof
.............\.......\mux8_1.tan.rpt
.............\.......\mux8_1.tan.summary
.............\.......\mux8_1.tcl
.............\.......\mux8_1.vhd
.............\.......\mux8_1.vwf
.............\.......\pins for mux8_1.txt
.............\Verilog File\mux8_1.v
.............\............\mux8_1_TB.v
.............\.HDL File\mux8_1.vhd
.............\Project\db
.............\Project
.............\Verilog File
.............\VHDL File
exp1.5_mux8_1

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