Using VHDL and verylog language 3_8 decoder function, you can achieve in Quartus

exp1.3_decoder3_8\decoder3_8.qsf
.................\Project\Block1.bdf
.................\.......\db\decoder3_8.asm.qmsg
.................\.......\..\decoder3_8.asm_labs.ddb
.................\.......\..\decoder3_8.cbx.xml
.................\.......\..\decoder3_8.cmp.bpm
.................\.......\..\decoder3_8.cmp.cdb
.................\.......\..\decoder3_8.cmp.ecobp
.................\.......\..\decoder3_8.cmp.hdb
.................\.......\..\decoder3_8.cmp.logdb
.................\.......\..\decoder3_8.cmp.rdb
.................\.......\..\decoder3_8.cmp.tdb
.................\.......\..\decoder3_8.cmp0.ddb
.................\.......\..\decoder3_8.cmp2.ddb
.................\.......\..\decoder3_8.db_info
.................\.......\..\decoder3_8.eco.cdb
.................\.......\..\decoder3_8.fit.qmsg
.................\.......\..\decoder3_8.hier_info
.................\.......\..\decoder3_8.hif
.................\.......\..\decoder3_8.map.bpm
.................\.......\..\decoder3_8.map.cdb
.................\.......\..\decoder3_8.map.ecobp
.................\.......\..\decoder3_8.map.hdb
.................\.......\..\decoder3_8.map.logdb
.................\.......\..\decoder3_8.map.qmsg
.................\.......\..\decoder3_8.map_bb.cdb
.................\.......\..\decoder3_8.map_bb.hdb
.................\.......\..\decoder3_8.map_bb.hdbx
.................\.......\..\decoder3_8.map_bb.logdb
.................\.......\..\decoder3_8.pre_map.cdb
.................\.......\..\decoder3_8.pre_map.hdb
.................\.......\..\decoder3_8.psp
.................\.......\..\decoder3_8.root_partition.cmp.atm
.................\.......\..\decoder3_8.root_partition.cmp.dfp
.................\.......\..\decoder3_8.root_partition.cmp.hdbx
.................\.......\..\decoder3_8.root_partition.cmp.logdb
.................\.......\..\decoder3_8.root_partition.cmp.rcf
.................\.......\..\decoder3_8.root_partition.map.atm
.................\.......\..\decoder3_8.root_partition.map.hdbx
.................\.......\..\decoder3_8.root_partition.map.info
.................\.......\..\decoder3_8.rtlv.hdb
.................\.......\..\decoder3_8.rtlv_sg.cdb
.................\.......\..\decoder3_8.rtlv_sg_swap.cdb
.................\.......\..\decoder3_8.sgdiff.cdb
.................\.......\..\decoder3_8.sgdiff.hdb
.................\.......\..\decoder3_8.signalprobe.cdb
.................\.......\..\decoder3_8.sld_design_entry.sci
.................\.......\..\decoder3_8.sld_design_entry_dsc.sci
.................\.......\..\decoder3_8.syn_hier_info
.................\.......\..\decoder3_8.tan.qmsg
.................\.......\..\decoder3_8.tis_db_list.ddb
.................\.......\..\decoder3_8.tmw_info
.................\.......\..\prev_cmp_decoder3_8.asm.qmsg
.................\.......\..\prev_cmp_decoder3_8.fit.qmsg
.................\.......\..\prev_cmp_decoder3_8.map.qmsg
.................\.......\..\prev_cmp_decoder3_8.qmsg
.................\.......\..\prev_cmp_decoder3_8.tan.qmsg
.................\.......\decoder3_8.asm.rpt
.................\.......\decoder3_8.bsf
.................\.......\decoder3_8.done
.................\.......\decoder3_8.dpf
.................\.......\decoder3_8.fit.rpt
.................\.......\decoder3_8.fit.smsg
.................\.......\decoder3_8.fit.summary
.................\.......\decoder3_8.flow.rpt
.................\.......\decoder3_8.map.rpt
.................\.......\decoder3_8.map.summary
.................\.......\decoder3_8.pin
.................\.......\decoder3_8.pof
.................\.......\decoder3_8.qpf
.................\.......\decoder3_8.qsf
.................\.......\decoder3_8.qws
.................\.......\decoder3_8.sof
.................\.......\decoder3_8.tan.rpt
.................\.......\decoder3_8.tan.summary
.................\.......\decoder3_8.tcl
.................\.......\decoder3_8.vhd
.................\.......\pins for decoder8_3.txt
.................\Verilog File\decoder3_8.v
.................\............\decoder3_8_TB.v
.................\.HDL File\decoder3_8.vhd
.................\Project\db
.................\Proj

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