full adder 4x4 for spartan 3 fpga

full_adder_44
.............\full_adder.v
.............\full_adder_44.bgn
.............\full_adder_44.bit
.............\full_adder_44.bld
.............\full_adder_44.cmd_log
.............\full_adder_44.drc
.............\full_adder_44.gise
.............\full_adder_44.lso
.............\full_adder_44.ncd
.............\full_adder_44.ngc
.............\full_adder_44.ngd
.............\full_adder_44.ngr
.............\full_adder_44.pad
.............\full_adder_44.par
.............\full_adder_44.pcf
.............\full_adder_44.prj
.............\full_adder_44.ptwx
.............\full_adder_44.stx
.............\full_adder_44.syr
.............\full_adder_44.twr
.............\full_adder_44.twx
.............\full_adder_44.unroutes
.............\full_adder_44.ut
.............\full_adder_44.v
.............\full_adder_44.xise
.............\full_adder_44.xpi
.............\full_adder_44.xst
.............\full_adder_44_bitgen.xwbt
.............\full_adder_44_envsettings.html
.............\full_adder_44_guide.ncd
.............\full_adder_44_map.map
.............\full_adder_44_map.mrp
.............\full_adder_44_map.ncd
.............\full_adder_44_map.ngm
.............\full_adder_44_map.xrpt
.............\full_adder_44_ngdbuild.xrpt
.............\full_adder_44_pad.csv
.............\full_adder_44_pad.txt
.............\full_adder_44_par.xrpt
.............\full_adder_44_summary.html
.............\full_adder_44_summary.xml
.............\full_adder_44_usage.xml
.............\full_adder_44_xst.xrpt
.............\ipcore_dir
.............\iseconfig
.............\.........\full_adder_44.projectmgr
.............\.........\full_adder_44.xreport
.............\tb_full_adder_44.fdo
.............\tb_full_adder_44.udo
.............\tb_full_adder_44.v
.............\tb_full_adder_44_wave.fdo
.............\transcript
.............\usage_statistics_webtalk.html
.............\vsim.wlf
.............\webtalk.log
.............\webtalk_pn.xml
.............\work
.............\....\full_adder
.............\....\..........\verilog.prw
.............\....\..........\verilog.psm
.............\....\..........\_primary.dat
.............\....\..........\_primary.dbs
.............\....\..........\_primary.vhd
.............\....\full_adder_44
.............\....\.............\verilog.prw
.............\....\.............\verilog.psm
.............\....\.............\_primary.dat
.............\....\.............\_primary.dbs
.............\....\.............\_primary.vhd
.............\....\glbl
.............\....\....\verilog.prw
.............\....\....\verilog.psm
.............\....\....\_primary.dat
.............\....\....\_primary.dbs
.............\....\....\_primary.vhd
.............\....\tb_full_adder_44
.............\....\................\verilog.prw
.............\....\................\verilog.psm
.............\....\................\_primary.dat
.............\....\................\_primary.dbs
.............\....\................\_primary.vhd
.............\....\_info
.............\....\_temp
.............\....\.....\vloghmy8nn
.............\....\_vmake
.............\xlnx_auto_0_xdb
.............\...............\cst.xbcd
.............\xst
.............\...\dump.xst
.............\...\........\full_adder_44.prj
.............\...\........\.................\ngx
.............\...\........\.................\...\notopt
.............\...\........\.................\...\opt
.............\...\projnav.tmp
.............\...\work
.............\...\....\hdllib.ref
.............\...\....\vlg5A
.............\...\....\.....\full__adder.bin
.............\...\....\vlg71

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