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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 33kb
  • Downloaded :0次
  • Author :g****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
A binary full subtractor design, respectively, schematic input and text input method, complete with a hierarchical design method
Packet file list
(Preview for download)
minus\Block1.bdf
.....\db\minus.db_info
.....\..\minus.eco.cdb
.....\..\minus.sim.cvwf
.....\..\minus.sld_design_entry.sci
.....\..\prev_cmp_minus.asm.qmsg
.....\..\prev_cmp_minus.fit.qmsg
.....\..\prev_cmp_minus.map.qmsg
.....\..\prev_cmp_minus.qmsg
.....\..\prev_cmp_minus.sim.qmsg
.....\..\prev_cmp_minus.tan.qmsg
.....\..\wed.wsf
.....\h_minus.bsf
.....\h_minus.vhd
.....\incremental_db\compiled_partitions\minus.root_partition.map.kpt
.....\..............\README
.....\minus.asm.rpt
.....\minus.done
.....\minus.fit.rpt
.....\minus.fit.summary
.....\minus.flow.rpt
.....\minus.map.rpt
.....\minus.map.summary
.....\minus.pin
.....\minus.qpf
.....\minus.qsf
.....\minus.qws
.....\minus.sim.rpt
.....\minus.tan.rpt
.....\minus.tan.summary
.....\minus.vhd
.....\minus.vhd.bak
.....\minus.vwf
.....\or2a.vhd
.....\or2a.vhd.bak
.....\incremental_db\compiled_partitions
.....\db
.....\incremental_db
minus
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