Fpga entry Experiment 1: light led lights. verilog syntax

Experiment01
............\db
............\..\prev_cmp_top_module.asm.qmsg
............\..\prev_cmp_top_module.fit.qmsg
............\..\prev_cmp_top_module.map.qmsg
............\..\prev_cmp_top_module.qmsg
............\..\prev_cmp_top_module.sim.qmsg
............\..\prev_cmp_top_module.tan.qmsg
............\..\top_module.asm.qmsg
............\..\top_module.asm_labs.ddb
............\..\top_module.cbx.xml
............\..\top_module.cmp.bpm
............\..\top_module.cmp.cdb
............\..\top_module.cmp.ecobp
............\..\top_module.cmp.hdb
............\..\top_module.cmp.kpt
............\..\top_module.cmp.logdb
............\..\top_module.cmp.rdb
............\..\top_module.cmp.tdb
............\..\top_module.cmp0.ddb
............\..\top_module.cmp2.ddb
............\..\top_module.cmp_merge.kpt
............\..\top_module.db_info
............\..\top_module.eco.cdb
............\..\top_module.eds_overflow
............\..\top_module.fit.qmsg
............\..\top_module.fnsim.hdb
............\..\top_module.fnsim.qmsg
............\..\top_module.hier_info
............\..\top_module.hif
............\..\top_module.lpc.html
............\..\top_module.lpc.rdb
............\..\top_module.lpc.txt
............\..\top_module.map.bpm
............\..\top_module.map.cdb
............\..\top_module.map.ecobp
............\..\top_module.map.hdb
............\..\top_module.map.kpt
............\..\top_module.map.logdb
............\..\top_module.map.qmsg
............\..\top_module.map_bb.cdb
............\..\top_module.map_bb.hdb
............\..\top_module.map_bb.logdb
............\..\top_module.pre_map.cdb
............\..\top_module.pre_map.hdb
............\..\top_module.rpp.qmsg
............\..\top_module.rtlv.hdb
............\..\top_module.rtlv_sg.cdb
............\..\top_module.rtlv_sg_swap.cdb
............\..\top_module.sgate.rvd
............\..\top_module.sgate_sm.rvd
............\..\top_module.sgdiff.cdb
............\..\top_module.sgdiff.hdb
............\..\top_module.sim.cvwf
............\..\top_module.sim.hdb
............\..\top_module.sim.qmsg
............\..\top_module.sim.rdb
............\..\top_module.sld_design_entry_dsc.sci
............\..\top_module.syn_hier_info
............\..\top_module.tan.qmsg
............\..\top_module.tis_db_list.ddb
............\..\top_module.tmw_info
............\..\top_module_global_asgn_op.abo
............\..\wed.wsf
............\incremental_db
............\..............\compiled_partitions
............\..............\...................\top_module.root_partition.cmp.atm
............\..............\...................\top_module.root_partition.cmp.dfp
............\..............\...................\top_module.root_partition.cmp.hdbx
............\..............\...................\top_module.root_partition.cmp.kpt
............\..............\...................\top_module.root_partition.cmp.logdb
............\..............\...................\top_module.root_partition.cmp.rcf
............\..............\...................\top_module.root_partition.map.atm
............\..............\...................\top_module.root_partition.map.dpi
............\..............\...................\top_module.root_partition.map.hdbx
............\..............\...................\top_module.root_partition.map.kpt
............\led0_module.asm.rpt
............\led0_module.cdf
............\led0_module.done
............\led0_module.dpf
............\led0_module.eda.rpt
............\led0_module.fit.rpt
............\led0_module.fit.summary
............\led0_module.flow.rpt
............\led0_module.map.rpt
............\led0_module.map.summary
............\led0_module.pin
............\led0_module.pof
............\led0_module.qpf
............\led0_module.qsf
............\led0_module.qws
............\led0_module.sof
............\led0_module.tan.rpt
............\led0_module.tan.summary
............\led0_module.v
............\led0_module.v.bak
............\led0_module_assignment_defaults.qdf
............\led1_module.v
............\led1_module.v.bak
............\led2_module.v

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．