Verilong language with simple 8 key keyboard, and downloaded to the FPGA simulation, to achieve functional

dianziqin\cmp_state.ini
.........\sim.cfg
.........\Speaker.vhd
.........\tone.vhd
.........\top.asm.rpt
.........\top.done
.........\top.fit.eqn
.........\top.fit.rpt
.........\top.fit.summary
.........\top.flow.rpt
.........\top.map.eqn
.........\top.map.rpt
.........\top.map.summary
.........\top.pin
.........\top.pof
.........\top.qpf
.........\top.qsf
.........\top.qws
.........\top.sim.rpt
.........\top.sof
.........\top.tan.rpt
.........\top.tan.summary
.........\top.vhd
.........\top.vwf
.........\top_assignment_defaults.qdf
.........\_desktop.ini
.........\db\altsyncram_dvk.tdf
.........\..\cntr_7t7.tdf
.........\..\cntr_ea7.tdf
.........\..\top.asm.qmsg
.........\..\top.cbx.xml
.........\..\top.cmp.cdb
.........\..\top.cmp.hdb
.........\..\top.cmp.rdb
.........\..\top.cmp.tdb
.........\..\top.cmp0.ddb
.........\..\top.dbp
.........\..\top.db_info
.........\..\top.eco.cdb
.........\..\top.fit.qmsg
.........\..\top.hier_info
.........\..\top.hif
.........\..\top.map.cdb
.........\..\top.map.hdb
.........\..\top.map.qmsg
.........\..\top.pre_map.cdb
.........\..\top.pre_map.hdb
.........\..\top.psp
.........\..\top.rtlv.hdb
.........\..\top.rtlv_sg.cdb
.........\..\top.rtlv_sg_swap.cdb
.........\..\top.sgdiff.cdb
.........\..\top.sgdiff.hdb
.........\..\top.signalprobe.cdb
.........\..\top.sld_design_entry.sci
.........\..\top.sld_design_entry_dsc.sci
.........\..\top.syn_hier_info
.........\..\top.tan.qmsg
.........\..\TOP0.rtl.mif
.........\..\_desktop.ini
.........\新建文件夹\readme.txt
.........\..........\_desktop.ini
.........\db
.........\新建文件夹
dianziqin

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