Composition of experimental computer operating 4, fpga development board, verilog language

09级计组实验_B班_31组_5090309744_谢聪_实验4代码\ipcore_dir\blk_mem_gen_ds512.pdf
...............................................\..........\datamemory.asy
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...............................................\..........\datamemory.xco
...............................................\..........\datamemory.xise
...............................................\..........\datamemory_flist.txt
...............................................\..........\datamemory_xmdf.tcl
...............................................\lab4.gise
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...............................................\lab4.xise
...............................................\...._xdb\tmp\ise\version
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...............................................\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
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...............................................\........\...\...\............\................Gui\CViewSelector
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...............................................\........\...\...\............\...................\Process-BehavioralSim-
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
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...............................................\........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-Pos

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