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Computer-Architecture-lab2

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 871kb
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  • Author :聪***
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Composition of experimental work computer 2, fpga development board, verilog language
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09级计组实验_B班_31组_5090309744_谢聪_实验2代码\counter.gise
...............................................\counter.ise
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...............................................\counter_1.v
...............................................\counter_guide.ncd
...............................................\counter_isim_beh.wdb
...............................................\counter_pa.log
...............................................\counter_pa_ports.v
...............................................\counter_summary.html
...............................................\........xdb\tmp\ise\version
...............................................\...........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
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...............................................\...........\...\...\............\..................\__stored_object_table__
...............................................\...........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...............................................\...........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...............................................\...........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...............................................\...........\...\...\............\................\................\dpm_project_main_StrTbl
...............................................\...........\...\...\............\................Gui\CViewSelector
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...............................................\...........\...\...\............\...................\File-SynthesisOnly
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...............................................\...........\...\...\............\...................\Library-SynthesisOnly
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...............................................\...........\...\...\............\...................\Process-BehavioralSim-
...............................................\...........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\...........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...............................................\...........\...\...\............\...................\Process-BehavioralSim-_StrTbl
...............................................\...........\...\...\............\...................\Process-PostRouteSim-
...............................................\...........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG
...............................................\...........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG_StrTbl
...............................................\...........\...\...\............\...................\Process-PostRouteSim-_StrTbl
...............................................\...........\...\...\............\...................\Process-SynthesisOnly-
...............................................\...........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF
...............................................\...........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl
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