this a inverse gate with lot s of other gates and testbench for novice

inverseuse_ex1\cellule_logique_virtuelle.bld
..............\cellule_logique_virtuelle.ncd
..............\cellule_logique_virtuelle.ngd
..............\cellule_logique_virtuelle.pad
..............\cellule_logique_virtuelle.par
..............\cellule_logique_virtuelle.pcf
..............\cellule_logique_virtuelle.ptwx
..............\cellule_logique_virtuelle.sch
..............\cellule_logique_virtuelle.twr
..............\cellule_logique_virtuelle.twx
..............\cellule_logique_virtuelle.udo
..............\cellule_logique_virtuelle.unroutes
..............\cellule_logique_virtuelle.vhf
..............\cellule_logique_virtuelle.xpi
..............\cellule_logique_virtuelle_guide.ncd
..............\cellule_logique_virtuelle_map.map
..............\cellule_logique_virtuelle_map.mrp
..............\cellule_logique_virtuelle_map.ncd
..............\cellule_logique_virtuelle_map.ngm
..............\cellule_logique_virtuelle_map.xrpt
..............\cellule_logique_virtuelle_ngdbuild.xrpt
..............\cellule_logique_virtuelle_pad.csv
..............\cellule_logique_virtuelle_pad.txt
..............\cellule_logique_virtuelle_par.xrpt
..............\cellule_logique_virtuelle_prev_built.ngd
..............\cellule_logique_virtuelle_summary.html
..............\cellule_logique_virtuelle_summary.xml
..............\cellule_logique_virtuelle_usage.xml
..............\cellule_logique_virtuelle_wave.fdo
..............\device_usage_statistics.html
..............\inv.bmp
..............\inv.do
..............\inv1.bmp
..............\inverseuse_ex1.gise
..............\inverseuse_ex1.ise
..............\inverseuse_ex1.ntrc_log
..............\inverseuse_ex1.xise
..............\inv_ex1.bgn
..............\inv_ex1.bit
..............\inv_ex1.bld
..............\inv_ex1.drc
..............\inv_ex1.ncd
..............\inv_ex1.ngd
..............\inv_ex1.pad
..............\inv_ex1.par
..............\inv_ex1.pcf
..............\inv_ex1.ptwx
..............\inv_ex1.sch
..............\inv_ex1.twr
..............\inv_ex1.twx
..............\inv_ex1.udo
..............\inv_ex1.unroutes
..............\inv_ex1.ut
..............\inv_ex1.vhf
..............\inv_ex1.xpi
..............\inv_ex1_guide.ncd
..............\inv_ex1_map.map
..............\inv_ex1_map.mrp
..............\inv_ex1_map.ncd
..............\inv_ex1_map.ngm
..............\inv_ex1_map.xrpt
..............\inv_ex1_ngdbuild.xrpt
..............\inv_ex1_pad.csv
..............\inv_ex1_pad.txt
..............\inv_ex1_par.xrpt
..............\inv_ex1_prev_built.ngd
..............\inv_ex1_summary.html
..............\inv_ex1_summary.xml
..............\inv_ex1_usage.xml
..............\inv_ex1_wave.fdo
..............\logic.do
..............\lut.do
..............\LUT.sch
..............\LUT.udo
..............\LUT.vhf
..............\LUT_summary.html
..............\LUT_wave.fdo
..............\modelsim.ini
..............\multi.do
..............\multiVHDL.cmd_log
..............\multiVHDL.fdo
..............\multiVHDL.lso
..............\multiVHDL.ngc
..............\multiVHDL.ngr
..............\multiVHDL.prj
..............\multiVHDL.stx
..............\multiVHDL.syr
..............\multiVHDL.udo
..............\multiVHDL.vhd
..............\multiVHDL.xst
..............\multiVHDL_summary.html
..............\multiVHDL_vhdl.prj
..............\multiVHDL_wave.fdo
..............\multiVHDL_xst.xrpt
..............\multi_ex4.bld
..............\multi_ex4.ncd
..............\multi_ex4.ngd
..............\multi_ex4.pad
..............\multi_ex4.par
..............\multi_ex4.pcf

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