FPGA test case, consists of ten experiments: digital clock, timer, etc.

test3\LIB.DLS
.....\seven_seg.acf
.....\seven_seg.fit
.....\seven_seg.hex
.....\seven_seg.hif
.....\seven_seg.mmf
.....\seven_seg.ndb
.....\seven_seg.pin
.....\seven_seg.pof
.....\seven_seg.rpt
.....\seven_seg.snf
.....\seven_seg.sof
.....\seven_seg.sym
.....\seven_seg.ttf
.....\seven_seg.v
.....\test3_1.acf
.....\test3_1.fit
.....\test3_1.gdf
.....\test3_1.hex
.....\test3_1.hif
.....\test3_1.mmf
.....\test3_1.ndb
.....\test3_1.pin
.....\test3_1.pof
.....\test3_1.rpt
.....\test3_1.snf
.....\test3_1.sof
.....\test3_1.ttf
.....\test3_2.acf
.....\test3_2.fit
.....\test3_2.gdf
.....\test3_2.hex
.....\test3_2.hif
.....\test3_2.mmf
.....\test3_2.ndb
.....\test3_2.pin
.....\test3_2.pof
.....\test3_2.rpt
.....\test3_2.snf
.....\test3_2.sof
.....\test3_2.ttf
.....\U0820541.DLS
....4\LIB.DLS
.....\md0_4.acf
.....\md0_4.fit
.....\md0_4.hex
.....\md0_4.hif
.....\md0_4.mmf
.....\md0_4.ndb
.....\md0_4.pin
.....\md0_4.pof
.....\md0_4.rpt
.....\md0_4.snf
.....\md0_4.sof
.....\md0_4.sym
.....\md0_4.ttf
.....\md0_4.v
.....\md0_b.acf
.....\md0_b.fit
.....\md0_b.hex
.....\md0_b.hif
.....\md0_b.mmf
.....\md0_b.ndb
.....\md0_b.pin
.....\md0_b.pof
.....\md0_b.rpt
.....\md0_b.snf
.....\md0_b.sof
.....\md0_b.sym
.....\md0_b.ttf
.....\md0_B.v
.....\md3_9.acf
.....\md3_9.fit
.....\md3_9.hex
.....\md3_9.hif
.....\md3_9.mmf
.....\md3_9.ndb
.....\md3_9.pin
.....\md3_9.pof
.....\md3_9.rpt
.....\md3_9.snf
.....\md3_9.sof
.....\md3_9.sym
.....\md3_9.ttf
.....\md3_9.v
.....\md3_f.acf
.....\md3_f.fit
.....\md3_f.hex
.....\md3_f.hif
.....\md3_f.mmf
.....\md3_f.ndb
.....\md3_f.pin
.....\md3_f.pof
.....\md3_f.rpt
.....\md3_f.snf
.....\md3_f.sof
.....\md3_f.sym
.....\md3_f.ttf
.....\md3_f.v
.....\sec.v

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