ETR uses a timer to achieve acquisition and recording the number of pulses

TIMER_ETR_OK\List\core_cm3.crf
............\....\core_cm3.d
............\....\core_cm3.o
............\....\ExtDll.iex
............\....\gpio.crf
............\....\gpio.d
............\....\gpio.o
............\....\hal.crf
............\....\hal.d
............\....\hal.o
............\....\main.crf
............\....\main.d
............\....\main.o
............\....\main.__i
............\....\misc.crf
............\....\misc.d
............\....\misc.o
............\....\nvic.crf
............\....\nvic.d
............\....\nvic.o
............\....\nvic.__i
............\....\rcc.crf
............\....\rcc.d
............\....\rcc.o
............\....\SPILCD.axf
............\....\SPILCD.htm
............\....\SPILCD.lnp
............\....\SPILCD.map
............\....\SPILCD.plg
............\....\SPILCD.sct
............\....\SPILCD.tra
............\....\startup_stm32f10x_md.d
............\....\startup_stm32f10x_md.lst
............\....\startup_stm32f10x_md.o
............\....\stm32f10x_adc.crf
............\....\stm32f10x_adc.d
............\....\stm32f10x_adc.o
............\....\stm32f10x_bkp.crf
............\....\stm32f10x_bkp.d
............\....\stm32f10x_bkp.o
............\....\stm32f10x_can.crf
............\....\stm32f10x_can.d
............\....\stm32f10x_can.o
............\....\stm32f10x_crc.crf
............\....\stm32f10x_crc.d
............\....\stm32f10x_crc.o
............\....\stm32f10x_dac.crf
............\....\stm32f10x_dac.d
............\....\stm32f10x_dac.o
............\....\stm32f10x_dbgmcu.crf
............\....\stm32f10x_dbgmcu.d
............\....\stm32f10x_dbgmcu.o
............\....\stm32f10x_dma.crf
............\....\stm32f10x_dma.d
............\....\stm32f10x_dma.o
............\....\stm32f10x_exti.crf
............\....\stm32f10x_exti.d
............\....\stm32f10x_exti.o
............\....\stm32f10x_flash.crf
............\....\stm32f10x_flash.d
............\....\stm32f10x_flash.o
............\....\stm32f10x_fsmc.crf
............\....\stm32f10x_fsmc.d
............\....\stm32f10x_fsmc.o
............\....\stm32f10x_gpio.crf
............\....\stm32f10x_gpio.d
............\....\stm32f10x_gpio.o
............\....\stm32f10x_i2c.crf
............\....\stm32f10x_i2c.d
............\....\stm32f10x_i2c.o
............\....\stm32f10x_it.crf
............\....\stm32f10x_it.d
............\....\stm32f10x_it.o
............\....\stm32f10x_it.__i
............\....\stm32f10x_iwdg.crf
............\....\stm32f10x_iwdg.d
............\....\stm32f10x_iwdg.o
............\....\stm32f10x_pwr.crf
............\....\stm32f10x_pwr.d
............\....\stm32f10x_pwr.o
............\....\stm32f10x_rcc.crf
............\....\stm32f10x_rcc.d
............\....\stm32f10x_rcc.o
............\....\stm32f10x_rtc.crf
............\....\stm32f10x_rtc.d
............\....\stm32f10x_rtc.o
............\....\stm32f10x_sdio.crf
............\....\stm32f10x_sdio.d
............\....\stm32f10x_sdio.o
............\....\stm32f10x_spi.crf
............\....\stm32f10x_spi.d
............\....\stm32f10x_spi.o
............\....\stm32f10x_tim.crf
............\....\stm32f10x_tim.d
............\....\stm32f10x_tim.o
............\....\stm32f10x_usart.crf
............\....\stm32f10x_usart.d
............\....\stm32f10x_usart.o
............\....\stm32f10x_wwdg.crf
............\....\stm32f10x_wwdg.d

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