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Entrega-P2

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 212kb
  • Downloaded :0次
  • Author :kale****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
implementation PWM for Robot in VHDL
Packet file list
(Preview for download)
posicio.vhd
test_7b.vhd
c7b_test.vhd
cclock_div_test.vhd
clock_cont_7b.vhd
clock_div.vhd
clock_divisor.vhd
clock_test.vhd
clock_total.vhd
clock_total_test.vhd
comparador.vhd
comparador_test.vhd
drive_motor.vhd
drive_motor_test.vhd
gen_polsos.vhd
gen_rampa.vhd
gen_rampa_test.vhd
Informe Pr卌tica 2.pdf
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