Altera ModelSim FPGA

TrafficLightController\clk_1hz_wave.do
......................\sourcecode\clk_1hz.v
......................\..........\clk_1hz.v.bak
......................\..........\comparator.v
......................\..........\HexDigit.v
......................\..........\traffic_controller.v
......................\..........\traffic_controller.v.bak
......................\..........\traffic_controller_map.v
......................\..........\traffic_controller_map.v.bak
......................\..........\traffic_controller_tb.v
......................\..........\traffic_controller_tb.v.bak
......................\TrafficLightController.cr.mti
......................\TrafficLightController.mpf
......................\vsim.wlf
......................\work\clk_1hz\verilog.prw
......................\....\.......\verilog.psm
......................\....\.......\verilog.rw
......................\....\.......\_primary.dat
......................\....\.......\_primary.dbs
......................\....\.......\_primary.vhd
......................\....\traffic_controller\verilog.prw
......................\....\..................\verilog.psm
......................\....\..................\verilog.rw
......................\....\..................\_primary.dat
......................\....\..................\_primary.dbs
......................\....\..................\_primary.vhd
......................\....\.................._map\verilog.prw
......................\....\......................\verilog.psm
......................\....\......................\verilog.rw
......................\....\......................\_primary.dat
......................\....\......................\_primary.dbs
......................\....\......................\_primary.vhd
......................\....\...................tb\verilog.prw
......................\....\.....................\verilog.psm
......................\....\.....................\verilog.rw
......................\....\.....................\_primary.dat
......................\....\.....................\_primary.dbs
......................\....\.....................\_primary.vhd
......................\....\_info
......................\....\_vmake
......................\....\clk_1hz
......................\....\traffic_controller
......................\....\traffic_controller_map
......................\....\traffic_controller_tb
......................\....\_temp
......................\sourcecode
......................\work
TrafficLightController

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