Procedures to achieve the data transmission between the FPGA internal RAM. Uses 3 RAM+RAM structure. Has passed through debugging

3ram_ram
........\auto_project.ipf
........\auto_project_1.ipf
........\auto_project_xdb
........\................\tmp
........\coregen.cgc
........\coregen.cgp
........\dcm1.tfi
........\dcm1.v
........\dcm1_arwz.ucf
........\ipcore_dir
........\..........\blk_mem_gen_ds512.pdf
........\..........\coregen.cgc
........\..........\coregen.cgp
........\..........\coregen.log
........\..........\coregen.rsp
........\..........\dcm1.cgc
........\..........\dcm1.cgp
........\..........\dcm1.v
........\..........\dcm1.xaw
........\..........\dcm1_arwz.ucf
........\..........\dcm1_flist.txt
........\..........\dcm1_readme.txt
........\..........\dcm1_xmdf.tcl
........\..........\fifo.cgc
........\..........\fifo.cgp
........\..........\fifo_generator_ug175.pdf
........\..........\fifo_ip.asy
........\..........\fifo_ip.cgc
........\..........\fifo_ip.cgp
........\..........\fifo_ip.gise
........\..........\fifo_ip.ngc
........\..........\fifo_ip.v
........\..........\fifo_ip.veo
........\..........\fifo_ip.vhd
........\..........\fifo_ip.vho
........\..........\fifo_ip.xco
........\..........\fifo_ip.xise
........\..........\fifo_ip_flist.txt
........\..........\fifo_ip_readme.txt
........\..........\fifo_ip_xmdf.tcl
........\..........\fif_ip.asy
........\..........\fif_ip.cgc
........\..........\fif_ip.cgp
........\..........\fif_ip.gise
........\..........\fif_ip.ngc
........\..........\fif_ip.v
........\..........\fif_ip.veo
........\..........\fif_ip.vhd
........\..........\fif_ip.vho
........\..........\fif_ip.xco
........\..........\fif_ip.xise
........\..........\fif_ip_flist.txt
........\..........\fif_ip_readme.txt
........\..........\fif_ip_xmdf.tcl
........\..........\RAM.asy
........\..........\RAM.cgc
........\..........\RAM.cgp
........\..........\RAM.gise
........\..........\RAM.ngc
........\..........\RAM.sym
........\..........\RAM.v
........\..........\RAM.veo
........\..........\RAM.vhd
........\..........\RAM.vho
........\..........\RAM.xco
........\..........\RAM.xco.bak
........\..........\RAM.xise
........\..........\RAM1.asy
........\..........\RAM1.cgc
........\..........\RAM1.cgp
........\..........\RAM1.gise
........\..........\RAM1.ngc
........\..........\RAM1.v
........\..........\RAM1.veo
........\..........\RAM1.vhd
........\..........\RAM1.vho
........\..........\RAM1.xco
........\..........\RAM1.xise
........\..........\RAM1_flist.txt
........\..........\RAM1_readme.txt
........\..........\RAM1_xmdf.tcl
........\..........\RAM_flist.txt
........\..........\RAM_readme.txt
........\..........\RAM_xmdf.tcl
........\..........\tmp
........\..........\...\_cg
........\..........\xaw2verilog.log
........\..........\xlnx_auto_0_xdb
........\..........\_xmsgs
........\..........\......\ngcbuild.xmsgs
........\..........\......\pn_parser.xmsgs
........\..........\......\xst.xmsgs
........\iseconfig
........\.........\led.projectmgr
........\.........\led.xreport
........\.........\main.xreport
........\led.bgn
........\led.bld
........\led.drc

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