This is a long frame sync clock generated Verilog source code, has been compiled by, can be used directly

Long frame synchronous clock\db\longframe1.asm.qmsg
............................\..\longframe1.asm_labs.ddb
............................\..\longframe1.cbx.xml
............................\..\longframe1.cmp.cdb
............................\..\longframe1.cmp.hdb
............................\..\longframe1.cmp.kpt
............................\..\longframe1.cmp.logdb
............................\..\longframe1.cmp.rdb
............................\..\longframe1.cmp.tdb
............................\..\longframe1.cmp0.ddb
............................\..\longframe1.cmp2.ddb
............................\..\longframe1.dbp
............................\..\longframe1.db_info
............................\..\longframe1.eco.cdb
............................\..\longframe1.fit.qmsg
............................\..\longframe1.hier_info
............................\..\longframe1.hif
............................\..\longframe1.map.cdb
............................\..\longframe1.map.hdb
............................\..\longframe1.map.logdb
............................\..\longframe1.map.qmsg
............................\..\longframe1.pre_map.cdb
............................\..\longframe1.pre_map.hdb
............................\..\longframe1.psp
............................\..\longframe1.rtlv.hdb
............................\..\longframe1.rtlv_sg.cdb
............................\..\longframe1.rtlv_sg_swap.cdb
............................\..\longframe1.sgdiff.cdb
............................\..\longframe1.sgdiff.hdb
............................\..\longframe1.signalprobe.cdb
............................\..\longframe1.sld_design_entry.sci
............................\..\longframe1.sld_design_entry_dsc.sci
............................\..\longframe1.syn_hier_info
............................\..\longframe1.tan.qmsg
............................\longframe1.asm.rpt
............................\longframe1.done
............................\longframe1.fit.rpt
............................\longframe1.fit.smsg
............................\longframe1.fit.summary
............................\longframe1.flow.rpt
............................\longframe1.map.rpt
............................\longframe1.map.summary
............................\longframe1.pin
............................\longframe1.pof
............................\longframe1.qpf
............................\longframe1.qsf
............................\longframe1.qws
............................\longframe1.sof
............................\longframe1.tan.rpt
............................\longframe1.tan.summary
............................\longframe1.v
............................\db
Long frame synchronous clock

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