VHDL-based four adder, operating environment quartus

adder4_1\adder4_1.done
........\adder4_1.fit.rpt
........\adder4_1.fit.summary
........\adder4_1.flow.rpt
........\adder4_1.map.rpt
........\adder4_1.map.summary
........\adder4_1.qpf
........\adder4_1.qsf
........\adder4_1.qws
........\adder4_1.vhd
........\adder4_1.vhd.bak
........\db\adder4_1.cbx.xml
........\..\adder4_1.cmp.bpm
........\..\adder4_1.cmp.cdb
........\..\adder4_1.cmp.hdb
........\..\adder4_1.cmp.logdb
........\..\adder4_1.cmp.rdb
........\..\adder4_1.dbp
........\..\adder4_1.db_info
........\..\adder4_1.eco.cdb
........\..\adder4_1.fit.qmsg
........\..\adder4_1.hier_info
........\..\adder4_1.hif
........\..\adder4_1.map.bpm
........\..\adder4_1.map.cdb
........\..\adder4_1.map.ecobp
........\..\adder4_1.map.hdb
........\..\adder4_1.map.logdb
........\..\adder4_1.map.qmsg
........\..\adder4_1.map_bb.cdb
........\..\adder4_1.map_bb.hdb
........\..\adder4_1.map_bb.logdb
........\..\adder4_1.pre_map.cdb
........\..\adder4_1.pre_map.hdb
........\..\adder4_1.psp
........\..\adder4_1.pss
........\..\adder4_1.rpp.qmsg
........\..\adder4_1.rtlv.hdb
........\..\adder4_1.rtlv_sg.cdb
........\..\adder4_1.rtlv_sg_swap.cdb
........\..\adder4_1.sgate.rvd
........\..\adder4_1.sgate_sm.rvd
........\..\adder4_1.sgdiff.cdb
........\..\adder4_1.sgdiff.hdb
........\..\adder4_1.sld_design_entry.sci
........\..\adder4_1.sld_design_entry_dsc.sci
........\..\adder4_1.syn_hier_info
........\..\adder4_1.tis_db_list.ddb
........\..\prev_cmp_adder4_1.fit.qmsg
........\..\prev_cmp_adder4_1.map.qmsg
........\..\prev_cmp_adder4_1.qmsg
........\db
adder4_1

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