Written in Verilog code, the serial port to send communications to achieve.

uart_T01\db\altsyncram_o1p3.tdf
........\..\altsyncram_q4p3.tdf
........\..\cntr_abi.tdf
........\..\cntr_dbi.tdf
........\..\cntr_e1j.tdf
........\..\cntr_q9i.tdf
........\..\cntr_uti.tdf
........\..\decode_aoi.tdf
........\..\decode_rqf.tdf
........\..\mux_aoc.tdf
........\..\mux_joc.tdf
........\..\prev_cmp_uart_T01.asm.qmsg
........\..\prev_cmp_uart_T01.eda.qmsg
........\..\prev_cmp_uart_T01.fit.qmsg
........\..\prev_cmp_uart_T01.map.qmsg
........\..\prev_cmp_uart_T01.qmsg
........\..\prev_cmp_uart_T01.sim.qmsg
........\..\prev_cmp_uart_T01.tan.qmsg
........\..\uart_T01.asm.qmsg
........\..\uart_T01.asm_labs.ddb
........\..\uart_T01.autos_3e92b2e5d298f5cf757a393f7655ccd81.cmp.atm
........\..\uart_T01.autos_3e92b2e5d298f5cf757a393f7655ccd81.cmp.logdb
........\..\uart_T01.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
........\..\uart_T01.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb
........\..\uart_T01.cbx.xml
........\..\uart_T01.cmp.bpm
........\..\uart_T01.cmp.cdb
........\..\uart_T01.cmp.ecobp
........\..\uart_T01.cmp.hdb
........\..\uart_T01.cmp.logdb
........\..\uart_T01.cmp.rdb
........\..\uart_T01.cmp.tdb
........\..\uart_T01.cmp0.ddb
........\..\uart_T01.cmp_bb.cdb
........\..\uart_T01.cmp_bb.hdb
........\..\uart_T01.cmp_bb.logdb
........\..\uart_T01.cmp_bb.rcf
........\..\uart_T01.dbp
........\..\uart_T01.db_info
........\..\uart_T01.eco.cdb
........\..\uart_T01.eda.qmsg
........\..\uart_T01.eds_overflow
........\..\uart_T01.fit.qmsg
........\..\uart_T01.fnsim.hdb
........\..\uart_T01.fnsim.qmsg
........\..\uart_T01.hier_info
........\..\uart_T01.hif
........\..\uart_T01.map.bpm
........\..\uart_T01.map.cdb
........\..\uart_T01.map.ecobp
........\..\uart_T01.map.hdb
........\..\uart_T01.map.logdb
........\..\uart_T01.map.qmsg
........\..\uart_T01.map_bb.cdb
........\..\uart_T01.map_bb.hdb
........\..\uart_T01.map_bb.logdb
........\..\uart_T01.pre_map.cdb
........\..\uart_T01.pre_map.hdb
........\..\uart_T01.psp
........\..\uart_T01.pss
........\..\uart_T01.rpp.qmsg
........\..\uart_T01.rtlv.hdb
........\..\uart_T01.rtlv_sg.cdb
........\..\uart_T01.rtlv_sg_swap.cdb
........\..\uart_T01.sgate.rvd
........\..\uart_T01.sgate_sm.rvd
........\..\uart_T01.sgdiff.cdb
........\..\uart_T01.sgdiff.hdb
........\..\uart_T01.signalprobe.cdb
........\..\uart_T01.sim.cvwf
........\..\uart_T01.sim.hdb
........\..\uart_T01.sim.qmsg
........\..\uart_T01.sim.rdb
........\..\uart_T01.simfam
........\..\uart_T01.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm
........\..\uart_T01.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.logdb
........\..\uart_T01.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
........\..\uart_T01.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb
........\..\uart_T01.sld_design_entry.sci
........\..\uart_T01.sld_design_entry_dsc.sci
........\..\uart_T01.syn_hier_info
........\..\uart_T01.tan.qmsg
........\..\uart_T01.tis_db_list.ddb
........\..\wed.wsf
........\simulation\modelsim\uart_T01.vo
........\..........\........\uart_T01_modelsim.xrf
........\..........\........\uart_T01_v.sdo
........\stp1.stp
........\test_uart.v
........\test_uart.v.bak
........\transcript
........\uart_R01.v
........\uart_R01.v.bak
........\uart_R01.vwf
........\uart_T01.asm.rpt
........\uart_T01.done
........\uart_T01.dpf
........\uart_T01.eda.rpt
........\uart_T01.fit.rpt
........\uart_T01.fit.smsg

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