Create a FIFO in the FPGA internal transmission test using the available buildings, can also be used for data transfer between two microcontrollers, but also upload a set of DSP-based FPGA' s SPI source

fifo
....\fifo.htm
....\fifo.txt
SPI
...\func_sim.do
...\post_sim.do
...\readme.doc
...\readme.txt
...\sck_logic.vhd
...\spi_control.zip
...\spi_control_sm.vhd
...\spi_interface.vhd
...\spi_master.cxt
...\spi_master.jed
...\spi_master.npl
...\spi_master.rpt
...\spi_master.vhd
...\spi_master_tb.vhd
...\spi_master_timesim.vhd
...\spi_rcv_shift_reg.vhd
...\spi_xmit_shift_reg.vhd
...\uc_interface.vhd
...\upcnt4.vhd
...\upcnt5.vhd
...\wave_color.do
...\wave_post_color.do
...\work
...\....\roc
...\....\...\roc_v.dat
...\....\...\roc_v.psm
...\....\...\_primary.dat
...\....\spi_master
...\....\..........\structure.dat
...\....\..........\structure.psm
...\....\..........\_primary.dat
...\....\testbench
...\....\.........\behavior.dat
...\....\.........\behavior.psm
...\....\.........\_primary.dat
...\....\_info

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