This document is in the company' s QUARTUS ALTERA under VHDL+ schematic written clock synchronization logic

clk_sync\clk_sync.asm.rpt
........\clk_sync.bdf
........\clk_sync.done
........\clk_sync.dpf
........\clk_sync.eda.rpt
........\clk_sync.fit.rpt
........\clk_sync.fit.smsg
........\clk_sync.fit.summary
........\clk_sync.flow.rpt
........\clk_sync.map.rpt
........\clk_sync.map.summary
........\clk_sync.pin
........\clk_sync.pof
........\clk_sync.qpf
........\clk_sync.qsf
........\clk_sync.qws
........\clk_sync.sim.rpt
........\clk_sync.sof
........\clk_sync.tan.rpt
........\clk_sync.tan.summary
........\clk_sync.vwf
........\clk_sync_nativelink_simulation.rpt
........\db\clk_sync.asm.qmsg
........\..\clk_sync.asm_labs.ddb
........\..\clk_sync.cbx.xml
........\..\clk_sync.cmp.cdb
........\..\clk_sync.cmp.ecobp
........\..\clk_sync.cmp.hdb
........\..\clk_sync.cmp.logdb
........\..\clk_sync.cmp.rdb
........\..\clk_sync.cmp.tdb
........\..\clk_sync.cmp0.ddb
........\..\clk_sync.cmp2.ddb
........\..\clk_sync.db_info
........\..\clk_sync.eco.cdb
........\..\clk_sync.eda.qmsg
........\..\clk_sync.eds_overflow
........\..\clk_sync.fit.qmsg
........\..\clk_sync.fnsim.hdb
........\..\clk_sync.fnsim.qmsg
........\..\clk_sync.hier_info
........\..\clk_sync.hif
........\..\clk_sync.map.cdb
........\..\clk_sync.map.ecobp
........\..\clk_sync.map.hdb
........\..\clk_sync.map.logdb
........\..\clk_sync.map.qmsg
........\..\clk_sync.map_bb.hdbx
........\..\clk_sync.map_bb.logdb
........\..\clk_sync.pre_map.cdb
........\..\clk_sync.pre_map.hdb
........\..\clk_sync.psp
........\..\clk_sync.root_partition.cmp.atm
........\..\clk_sync.root_partition.cmp.dfp
........\..\clk_sync.root_partition.cmp.hdbx
........\..\clk_sync.root_partition.cmp.logdb
........\..\clk_sync.root_partition.cmp.rcf
........\..\clk_sync.root_partition.map.atm
........\..\clk_sync.root_partition.map.hdbx
........\..\clk_sync.root_partition.map.info
........\..\clk_sync.rtlv.hdb
........\..\clk_sync.rtlv_sg.cdb
........\..\clk_sync.rtlv_sg_swap.cdb
........\..\clk_sync.sgdiff.cdb
........\..\clk_sync.sgdiff.hdb
........\..\clk_sync.signalprobe.cdb
........\..\clk_sync.sim.cvwf
........\..\clk_sync.sim.hdb
........\..\clk_sync.sim.qmsg
........\..\clk_sync.sim.rdb
........\..\clk_sync.simfam
........\..\clk_sync.sld_design_entry.sci
........\..\clk_sync.sld_design_entry_dsc.sci
........\..\clk_sync.syn_hier_info
........\..\clk_sync.tan.qmsg
........\..\clk_sync.tis_db_list.ddb
........\..\clk_sync.tmw_info
........\..\prev_cmp_clk_sync.asm.qmsg
........\..\prev_cmp_clk_sync.eda.qmsg
........\..\prev_cmp_clk_sync.fit.qmsg
........\..\prev_cmp_clk_sync.map.qmsg
........\..\prev_cmp_clk_sync.qmsg
........\..\prev_cmp_clk_sync.sim.qmsg
........\..\prev_cmp_clk_sync.tan.qmsg
........\..\wed.wsf
........\lpm_dff0.bsf
........\lpm_dff0.cmp
........\lpm_dff0.qip
........\lpm_dff0.vhd
........\simulation\modelsim\clk_sync.sft
........\..........\........\clk_sync.vho
........\..........\........\clk_sync.vht
........\..........\........\clk_sync_modelsim.xrf
........\..........\........\clk_sync_run_msim_gate_vhdl.do
........\..........\........\clk_sync_run_msim_gate_vhdl.do.bak
........\..........\........\gate_work\clk_sync\structure.dat
........\..........\........\.........\........\structure.psm
........\..........\........\.........\........\_primary.dat
........\..........\........\.........\........_vhd_tst\_primary.dat
........\..........\........\.........\_info

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．