written spi flash controller verilog

isp_top
.......\control.v
.......\control.v.bak
.......\db
.......\..\isp_top.cbx.xml
.......\..\isp_top.cmp.rdb
.......\..\isp_top.db_info
.......\..\isp_top.eco.cdb
.......\..\isp_top.hif
.......\..\isp_top.map.qmsg
.......\..\isp_top.map_bb.hdb
.......\..\isp_top.sld_design_entry.sci
.......\..\isp_top.tis_db_list.ddb
.......\..\prev_cmp_isp_top.map.qmsg
.......\..\prev_cmp_isp_top.qmsg
.......\divider.v
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\README
.......\isp_top.done
.......\isp_top.flow.rpt
.......\isp_top.map.rpt
.......\isp_top.map.smsg
.......\isp_top.map.summary
.......\isp_top.qpf
.......\isp_top.qsf
.......\isp_top.qws
.......\isp_top.v
.......\isp_top.v.bak
.......\rxd.v
.......\spi_clgen.v
.......\spi_defines.v
.......\spi_shift.v
.......\spi_top.bsf
.......\spi_top.v
.......\timescale.v
.......\txd.v
.......\uart.top
.......\uart_top.bsf
.......\uart_top.v
.......\wb_master_model.bsf
.......\wb_master_model.v
.......\wb_master_model.v.bak

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