Xia Yuwen teacher book EEPROM, including EEPROM, EEPROM_RW, SOURCE, TOP, I2C, etc. for testing only. Can not be integrated

EEPROM\addr.dat
......\addr.dat.bak
......\data.dat
......\data.dat.bak
......\.b\EEPROM.analyze_file.qmsg
......\..\EEPROM.cbx.xml
......\..\EEPROM.cmp.rdb
......\..\EEPROM.db_info
......\..\EEPROM.hif
......\..\EEPROM.map.qmsg
......\..\EEPROM.map_bb.hdb
......\..\EEPROM.ram0_EEPROM_8f0d2b8f.hdl.mif
......\..\EEPROM.sld_design_entry.sci
......\..\EEPROM.smart_action.txt
......\..\EEPROM.tis_db_list.ddb
......\..\logic_util_heursitic.dat
......\..\prev_cmp_EEPROM.qmsg
......\EEPROM.cr.mti
......\eeprom.dat
......\EEPROM.done
......\EEPROM.flow.rpt
......\EEPROM.map.rpt
......\EEPROM.map.smsg
......\EEPROM.map.summary
......\EEPROM.mpf
......\EEPROM.qsf
......\EEPROM.v
......\EEPROM.v.bak
......\EEPROM_WR.v
......\Signal.v
......\Top.v
......\top.v.bak
......\vsim.wlf
......\work\@e@e@p@r@o@m\verilog.asm
......\....\............\_primary.dat
......\....\............\_primary.vhd
......\....\............_@w@r\verilog.asm
......\....\.................\_primary.dat
......\....\.................\_primary.vhd
......\....\.signal\verilog.asm
......\....\.......\_primary.dat
......\....\.......\_primary.vhd
......\....\.top\verilog.asm
......\....\....\_primary.dat
......\....\....\_primary.vhd
......\....\_info
......\....\.opt\work_@signal_fast.asm
......\....\....\work_@signal_fast.dt2
......\....\....\work__info
......\....\....\_deps
......\....\@e@e@p@r@o@m
......\....\@e@e@p@r@o@m_@w@r
......\....\@signal
......\....\@top
......\....\_opt
......\....\_temp
......\db
......\work
EEPROM

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