Started: VHDL language and how to describe the door, and the right to master the VHDL language specification writing

and_gate\and_gate.asm.rpt
........\and_gate.done
........\and_gate.eda.rpt
........\and_gate.fit.rpt
........\and_gate.fit.summary
........\and_gate.flow.rpt
........\and_gate.map.rpt
........\and_gate.map.summary
........\and_gate.pin
........\and_gate.pof
........\and_gate.qpf
........\and_gate.qsf
........\and_gate.qws
........\and_gate.sim.rpt
........\and_gate.tan.rpt
........\and_gate.tan.summary
........\and_gate.vhd
........\and_gate.vhd.bak
........\and_gate.vwf
........\and_gate_nativelink_simulation.rpt
........\db\and_gate.asm.qmsg
........\..\and_gate.asm.rdb
........\..\and_gate.cbx.xml
........\..\and_gate.cmp.cdb
........\..\and_gate.cmp.hdb
........\..\and_gate.cmp.logdb
........\..\and_gate.cmp.rdb
........\..\and_gate.cmp.tdb
........\..\and_gate.cmp0.ddb
........\..\and_gate.db_info
........\..\and_gate.eco.cdb
........\..\and_gate.eda.qmsg
........\..\and_gate.eds_overflow
........\..\and_gate.fit.qmsg
........\..\and_gate.fnsim.hdb
........\..\and_gate.fnsim.qmsg
........\..\and_gate.hier_info
........\..\and_gate.hif
........\..\and_gate.lpc.html
........\..\and_gate.lpc.rdb
........\..\and_gate.lpc.txt
........\..\and_gate.map.cdb
........\..\and_gate.map.hdb
........\..\and_gate.map.logdb
........\..\and_gate.map.qmsg
........\..\and_gate.pre_map.cdb
........\..\and_gate.pre_map.hdb
........\..\and_gate.rtlv.hdb
........\..\and_gate.rtlv_sg.cdb
........\..\and_gate.rtlv_sg_swap.cdb
........\..\and_gate.sgdiff.cdb
........\..\and_gate.sgdiff.hdb
........\..\and_gate.sim.cvwf
........\..\and_gate.sim.hdb
........\..\and_gate.sim.qmsg
........\..\and_gate.sim.rdb
........\..\and_gate.sld_design_entry.sci
........\..\and_gate.sld_design_entry_dsc.sci
........\..\and_gate.smart_action.txt
........\..\and_gate.syn_hier_info
........\..\and_gate.tan.qmsg
........\..\and_gate.tis_db_list.ddb
........\..\and_gate.tmw_info
........\..\logic_util_heursitic.dat
........\..\mux_ebc.tdf
........\..\prev_cmp_and_gate.asm.qmsg
........\..\prev_cmp_and_gate.eda.qmsg
........\..\prev_cmp_and_gate.fit.qmsg
........\..\prev_cmp_and_gate.map.qmsg
........\..\prev_cmp_and_gate.qmsg
........\..\prev_cmp_and_gate.sim.qmsg
........\..\prev_cmp_and_gate.tan.qmsg
........\..\wed.wsf
........\incremental_db\compiled_partitions\and_gate.root_partition.map.kpt
........\..............\README
........\simulation\modelsim\and_gate.sft
........\..........\........\and_gate.vho
........\..........\........\and_gate_modelsim.xrf
........\..........\........\and_gate_vhd.sdo
........\Waveform1.vwf
........\Waveform2.vwf
........\Waveform3.vwf
........\incremental_db\compiled_partitions
........\simulation\modelsim
........\db
........\incremental_db
........\simulation
and_gate

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