This document details the implementation of an LCD controller in an Altera® MAX® II CPLD.

LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\code
.................................................\....\lcd_controller.v
.................................................\modelsim
.................................................\........\lcd_controller.cr.mti
.................................................\........\lcd_controller.mpf
.................................................\........\lcd_controller.v
.................................................\........\lcd_testbench.v
.................................................\........\transcript
.................................................\........\vsim.wlf
.................................................\........\wave.bmp
.................................................\........\wave.do
.................................................\........\work
.................................................\........\....\@u@f@m2
.................................................\........\....\.......\verilog.psm
.................................................\........\....\.......\_primary.dat
.................................................\........\....\.......\_primary.vhd
.................................................\........\....\@u@f@m2_altufm_parallel_bmm
.................................................\........\....\...........................\verilog.psm
.................................................\........\....\...........................\_primary.dat
.................................................\........\....\...........................\_primary.vhd
.................................................\........\....\divider
.................................................\........\....\.......\verilog.psm
.................................................\........\....\.......\_primary.dat
.................................................\........\....\.......\_primary.vhd
.................................................\........\....\fsm
.................................................\........\....\...\verilog.psm
.................................................\........\....\...\_primary.dat
.................................................\........\....\...\_primary.vhd
.................................................\........\....\lcd_controller
.................................................\........\....\..............\verilog.psm
.................................................\........\....\..............\_primary.dat
.................................................\........\....\..............\_primary.vhd
.................................................\........\....\lcd_testbench
.................................................\........\....\.............\verilog.psm
.................................................\........\....\.............\_primary.dat
.................................................\........\....\.............\_primary.vhd
.................................................\........\....\_info
.................................................\quartus
.................................................\.......\db
.................................................\.......\..\lcd_controller.db_info
.................................................\.......\..\lcd_controller.eco.cdb
.................................................\.......\..\lcd_controller.sld_design_entry.sci
.................................................\.......\..\prev_cmp_lcd_controller.map.qmsg
.................................................\.......\..\prev_cmp_lcd_controller.qmsg
.................................................\.......\lcd_controller.asm.rpt
.................................................\.......\lcd_controller.cdf
.................................................\.......\lcd_controller.done
.................................................\.......\lcd_controller.dpf
.................................................\.......\lcd_controller.fit.rpt
.................................................\.......\lcd_controller.fit.smsg
.................................................\.......\lcd_controller.fit.

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