The program is 3 divider using VHDL language design

deccount3\cmp_state.ini
.........\counter.bdf
.........\deccount.asm.rpt
.........\deccount.done
.........\deccount.fit.eqn
.........\deccount.fit.rpt
.........\deccount.fit.summary
.........\deccount.flow.rpt
.........\deccount.map.eqn
.........\deccount.map.rpt
.........\deccount.map.summary
.........\deccount.pin
.........\deccount.pof
.........\deccount.qpf
.........\deccount.qsf
.........\deccount.qws
.........\deccount.sim.rpt
.........\deccount.sof
.........\deccount.tan.rpt
.........\deccount.tan.summary
.........\deccount.vhd
.........\deccount.vwf
.........\lpm_count.bsf
.........\lpm_count.cmp
.........\lpm_count.vhd
.........\lpm_count_wave0.jpg
.........\lpm_count_waveforms.html
.........\db\cntr_ia8.tdf
.........\..\deccount.asm.qmsg
.........\..\deccount.cbx.xml
.........\..\deccount.cmp.cdb
.........\..\deccount.cmp.hdb
.........\..\deccount.cmp.rdb
.........\..\deccount.cmp.tdb
.........\..\deccount.cmp0.ddb
.........\..\deccount.db_info
.........\..\deccount.eco.cdb
.........\..\deccount.eds_overflow
.........\..\deccount.fit.qmsg
.........\..\deccount.hier_info
.........\..\deccount.hif
.........\..\deccount.map.cdb
.........\..\deccount.map.hdb
.........\..\deccount.map.qmsg
.........\..\deccount.pre_map.cdb
.........\..\deccount.pre_map.hdb
.........\..\deccount.psp
.........\..\deccount.rtlv.hdb
.........\..\deccount.rtlv_sg.cdb
.........\..\deccount.rtlv_sg_swap.cdb
.........\..\deccount.sgdiff.cdb
.........\..\deccount.sgdiff.hdb
.........\..\deccount.signalprobe.cdb
.........\..\deccount.sim.hdb
.........\..\deccount.sim.qmsg
.........\..\deccount.sim.rdb
.........\..\deccount.sim.vwf
.........\..\deccount.sld_design_entry.sci
.........\..\deccount.sld_design_entry_dsc.sci
.........\..\deccount.syn_hier_info
.........\..\deccount.tan.qmsg
.........\..\deccount_cmp.qrpt
.........\..\deccount_sim.qrpt
.........\db
deccount3

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