Because altera company' s CRC generation and checking modules do not support the use of the system Cyclone IV E series FPGA, so this independent design of the CRC module. The module' s interface with the CRC module interface altera' s basically the same, capable of 16-bit input data stream of CRC generation and checking. In this paper, CRC-CCITT generation entry, its expression is: X16+ X12+ X5+ X0. This module requires startp signal and endp signal indicating the start and end of data transmission. This module is a state machine design, and data for the end of the first data were handled by different states. In this module, use the for loop, which consumes more FPGA resources, but temporarily did not find any other ways to improve.

MY_IP\FIFO_READ_16bit.v
.....\FIFO_READ_16bit_hw.tcl
.....\FIFO_WRITE_16bit.v
.....\FIFO_WRITE_16bit_hw.tcl
MY_IP

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