MIMO Simulation VHDL code

multipliers\readme_multipliers_verilog.txt
...........\verilog
...........\.......\MAGNTD_18.v
...........\.......\mult17x17_u.v
...........\.......\MULT18X18.v
...........\.......\mult4x4_s.v
...........\.......\mult4x4_u.v
...........\.......\mult8x8_s.v
...........\.......\mult8x8_u.v
...........\.......\signed_mult_18x18.v
...........\.......\signed_mult_4x4_rr.v
...........\.......\signed_mult_8x8_rr.v
...........\.......\TWOS_CMP18.v
...........\.......\TWOS_CMP9.v
...........\.......\unsigned_mult_17x17_rr.v
...........\.......\unsigned_mult_4x4_rr.v
...........\.......\unsigned_mult_8x8_rr.v
multipliers
clock\readme_clock_verilog.txt
.....\verilog
.....\.......\BUFGCE_1_SUBM.v
.....\.......\BUFGCE_SUBM.v
.....\.......\BUFGMUX_1_INST.v
.....\.......\BUFGMUX_INST.v
clock
dcm\readme_dcm_verilog.txt
...\verilog
...\.......\BUFG_CLK0_FB_SUBM.v
...\.......\BUFG_CLK0_SUBM.v
...\.......\BUFG_CLK2X_FB_SUBM.v
...\.......\BUFG_CLK2X_SUBM.v
...\.......\BUFG_CLKDV_SUBM.v
...\.......\BUFG_DFS_FB_SUBM.v
...\.......\BUFG_DFS_SUBM.v
...\.......\BUFG_PHASE_CLK0_SUBM.v
...\.......\BUFG_PHASE_CLK2X_SUBM.v
...\.......\BUFG_PHASE_CLKDV_SUBM.v
...\.......\BUFG_PHASE_CLKFX_FB_SUBM.v
...\.......\DCM_INST.v
dcm
.dr\readme_ddr_verilog.txt
...\verilog
...\.......\DDR_3state.v
...\.......\DDR_Input.v
...\.......\DDR_Output.v
ddr
.istributed_ram\readme_distributed_ram_verilog.txt
...............\verilog
...............\.......\SelectRAM_128S.v
...............\.......\SelectRAM_16D.v
...............\.......\SelectRAM_16S.v
...............\.......\SelectRAM_32D.v
...............\.......\SelectRAM_32S.v
...............\.......\SelectRAM_64D.v
...............\.......\SelectRAM_64S.v
...............\.......\XC2V_DISTRI_RAM_64S.v
...............\.......\XC2V_RAM128XN_S.v
...............\.......\XC2V_RAM16XN_D.v
...............\.......\XC2V_RAM16XN_S.v
...............\.......\XC2V_RAM32XN_D.v
...............\.......\XC2V_RAM32XN_S.v
...............\.......\XC2V_RAM64XN_D.v
...............\.......\XC2V_RAM64XN_S.v
distributed_ram
lvds\readme_lvds_verilog.txt
....\verilog
....\.......\DDR_LVDS_3STATE.v
....\.......\DDR_LVDS_IN.v
....\.......\DDR_LVDS_OUT.v
lvds
multiplexers\readme_multiplexers_verilog.txt
............\verilog
............\.......\MUX_16_1.v
............\.......\MUX_2_1.v
............\.......\MUX_32_1.v
............\.......\MUX_4_1.v
............\.......\MUX_8_1.v
multiplexers
blockram\readme_blockram_verilog.txt
........\verilog
........\.......\SelectRAM_A1.v
........\.......\SelectRAM_A18.v
........\.......\SelectRAM_A18_B18.v
........\.......\SelectRAM_A18_B36.v
........\.......\SelectRAM_A1_B1.v
........\.......\SelectRAM_A1_B18.v
........\.......\SelectRAM_A1_B2.v
........\.......\SelectRAM_A1_B36.v
........\.......\SelectRAM_A1_B4.v
........\.......\SelectRAM_A1_B9.v
........\.......\SelectRAM_A2.v
........\.......\SelectRAM_A2_B18.v
........\.......\SelectRAM_A2_B2.v
........\.......\SelectRAM_A2_B36.v
........\.......\SelectRAM_A2_B4.v
........\.......\SelectRAM_A2_B9.v
........\.......\SelectRAM_A36.v
........\.......\SelectRAM_A36_B36.v
........\.......\SelectRAM_A4.v
........\.......\SelectRAM_A4_B18.v

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