the verilog of D flip flop bottom_top architecture

1_d_ff_bottom_top\cmp_state.ini
.................\db\d_ff_bottom_top-sim.vwf
.................\..\d_ff_bottom_top.asm.qmsg
.................\..\d_ff_bottom_top.cbx.xml
.................\..\d_ff_bottom_top.cmp.cdb
.................\..\d_ff_bottom_top.cmp.hdb
.................\..\d_ff_bottom_top.cmp.logdb
.................\..\d_ff_bottom_top.cmp.rdb
.................\..\d_ff_bottom_top.cmp.tdb
.................\..\d_ff_bottom_top.cmp0.ddb
.................\..\d_ff_bottom_top.db_info
.................\..\d_ff_bottom_top.eco.cdb
.................\..\d_ff_bottom_top.eds_overflow
.................\..\d_ff_bottom_top.fit.qmsg
.................\..\d_ff_bottom_top.fnsim.cdb
.................\..\d_ff_bottom_top.fnsim.hdb
.................\..\d_ff_bottom_top.fnsim.qmsg
.................\..\d_ff_bottom_top.hier_info
.................\..\d_ff_bottom_top.hif
.................\..\d_ff_bottom_top.map.cdb
.................\..\d_ff_bottom_top.map.hdb
.................\..\d_ff_bottom_top.map.logdb
.................\..\d_ff_bottom_top.map.qmsg
.................\..\d_ff_bottom_top.pre_map.cdb
.................\..\d_ff_bottom_top.pre_map.hdb
.................\..\d_ff_bottom_top.rtlv.hdb
.................\..\d_ff_bottom_top.rtlv_sg.cdb
.................\..\d_ff_bottom_top.rtlv_sg_swap.cdb
.................\..\d_ff_bottom_top.sgdiff.cdb
.................\..\d_ff_bottom_top.sgdiff.hdb
.................\..\d_ff_bottom_top.signalprobe.cdb
.................\..\d_ff_bottom_top.sim.cvwf
.................\..\d_ff_bottom_top.sim.hdb
.................\..\d_ff_bottom_top.sim.qmsg
.................\..\d_ff_bottom_top.sim.rdb
.................\..\d_ff_bottom_top.simfam
.................\..\d_ff_bottom_top.sld_design_entry.sci
.................\..\d_ff_bottom_top.sld_design_entry_dsc.sci
.................\..\d_ff_bottom_top.syn_hier_info
.................\..\d_ff_bottom_top.tan.qmsg
.................\..\d_ff_bottom_top.tis_db_list.ddb
.................\..\d_ff_bottom_top.tmw_info
.................\..\d_ff_bottom_top_cmp.qrpt
.................\..\d_ff_bottom_top_hier_info
.................\..\d_ff_bottom_top_sim.qrpt
.................\..\d_ff_bottom_top_syn_hier_info
.................\..\prev_cmp_d_ff_bottom_top.qmsg
.................\..\prev_cmp_d_ff_bottom_top.sim.qmsg
.................\..\wed.wsf
.................\d_ff_bottom_top.asm.rpt
.................\d_ff_bottom_top.bdf
.................\d_ff_bottom_top.bsf
.................\d_ff_bottom_top.done
.................\d_ff_bottom_top.dpf
.................\d_ff_bottom_top.fit.eqn
.................\d_ff_bottom_top.fit.rpt
.................\d_ff_bottom_top.fit.smsg
.................\d_ff_bottom_top.fit.summary
.................\d_ff_bottom_top.flow.rpt
.................\d_ff_bottom_top.map.eqn
.................\d_ff_bottom_top.map.rpt
.................\d_ff_bottom_top.map.summary
.................\d_ff_bottom_top.pin
.................\d_ff_bottom_top.pof
.................\d_ff_bottom_top.qpf
.................\d_ff_bottom_top.qsf
.................\d_ff_bottom_top.qws
.................\d_ff_bottom_top.sim.rpt
.................\d_ff_bottom_top.sof
.................\d_ff_bottom_top.tan.rpt
.................\d_ff_bottom_top.tan.summary
.................\d_ff_bottom_top.vwf
.................\d_ff_bottom_top_assignment_defaults.qdf
.................\d_ff_bottom_top_main.bdf
.................\FREQMOD2.V
.................\sim.cfg

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