FPGA-based Uart, baud rate selectable 2400/4800/96

07詹万鹏_Uart_FPGA\include.h
..................\init_device.c
..................\init_device.LST
..................\init_device.OBJ
..................\interrupts_init.c
..................\interrupts_init.LST
..................\interrupts_init.OBJ
..................\main.c
..................\main.LST
..................\main.OBJ
..................\oscillator_init.c
..................\oscillator_init.LST
..................\oscillator_init.OBJ
..................\port_io_init.c
..................\port_io_init.LST
..................\port_io_init.OBJ
..................\STARTUP.A51
..................\STARTUP.LST
..................\STARTUP.OBJ
..................\timer0_isr.c
..................\timer0_isr.LST
..................\timer0_isr.OBJ
..................\timer_init.c
..................\timer_init.LST
..................\timer_init.OBJ
..................\Uart0
..................\Uart0.hex
..................\Uart0.lnp
..................\Uart0.M51
..................\Uart0.Opt
..................\Uart0.plg
..................\Uart0.Uv2
..................\Uart0_Opt.Bak
..................\Uart0_Uv2.Bak
..................\uart_init.c
..................\uart_init.LST
..................\uart_init.OBJ
..................\uart_isr.c
..................\uart_isr.LST
..................\uart_isr.OBJ
07詹万鹏_Uart_FPGA

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